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Pankaj Gupta74f7b142020-12-09 14:02:38 +05301/*
Pankaj Gupta7834b462021-03-25 15:15:52 +05302 * Copyright 2020-2021 NXP
Pankaj Gupta74f7b142020-12-09 14:02:38 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8#ifndef DCFG_LSCH3_H
9#define DCFG_LSCH3_H
10
11/* dcfg block register offsets and bitfields */
12#define DCFG_PORSR1_OFFSET 0x00
13
14#define DCFG_DEVDISR1_OFFSET 0x70
15#define DCFG_DEVDISR1_SEC (1 << 22)
16
17#define DCFG_DEVDISR2_OFFSET 0x74
18
19#define DCFG_DEVDISR3_OFFSET 0x78
20#define DCFG_DEVDISR3_QBMAIN (1 << 12)
21
22#define DCFG_DEVDISR4_OFFSET 0x7C
23#define DCFG_DEVDISR4_SPI_QSPI (1 << 4 | 1 << 5)
24
25#define DCFG_DEVDISR5_OFFSET 0x80
26#define DISR5_DDRC1_MASK 0x1
27#define DISR5_DDRC2_MASK 0x2
28#define DISR5_OCRAM_MASK 0x1000
29#define DEVDISR5_MASK_ALL_MEM 0x00001003
30#define DEVDISR5_MASK_DDR 0x00000003
31#define DEVDISR5_MASK_DBG 0x00000400
32
33#define DCFG_DEVDISR6_OFFSET 0x84
34//#define DEVDISR6_MASK 0x00000001
35
36#define DCFG_COREDISR_OFFSET 0x94
37
38#define DCFG_SVR_OFFSET 0x0A4
39#define SVR_MFR_ID_MASK 0xF0000000
40#define SVR_MFR_ID_SHIFT 28
41#define SVR_FAMILY_MASK 0xF000000
42#define SVR_FAMILY_SHIFT 24
43#define SVR_DEV_ID_MASK 0x3F0000
44#define SVR_DEV_ID_SHIFT 16
45#define SVR_PERSONALITY_MASK 0x3E00
46#define SVR_PERSONALITY_SHIFT 9
47#define SVR_SEC_MASK 0x100
48#define SVR_SEC_SHIFT 8
49#define SVR_MAJ_VER_MASK 0xF0
50#define SVR_MAJ_VER_SHIFT 4
51#define SVR_MIN_VER_MASK 0xF
52
53#define RCWSR0_OFFSET 0x100
54#define RCWSR0_SYS_PLL_RAT_SHIFT 2
55#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
56#define RCWSR0_MEM_PLL_RAT_SHIFT 10
57#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
58#define RCWSR0_MEM2_PLL_RAT_SHIFT 18
59#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f
60
61#define RCWSR5_OFFSET 0x110
62#define RCWSR9_OFFSET 0x120
63#define RCWSR_SB_EN_OFFSET RCWSR9_OFFSET
64#define RCWSR_SBEN_MASK 0x1
65#define RCWSR_SBEN_SHIFT 10
66
67#define RCW_SR27_OFFSET 0x168
68/* DCFG register to dump error code */
69#define DCFG_SCRATCH4_OFFSET 0x20C
70#define DCFG_SCRATCHRW5_OFFSET 0x210
71#define DCFG_SCRATCHRW6_OFFSET 0x214
72#define DCFG_SCRATCHRW7_OFFSET 0x218
73#define DCFG_BOOTLOCPTRL_OFFSET 0x400
74#define DCFG_BOOTLOCPTRH_OFFSET 0x404
75#define DCFG_COREDISABLEDSR_OFFSET 0x990
76
Jiafei Pan67a98902021-09-10 19:10:47 +080077/* Reset module bit field */
78#define RSTCR_RESET_REQ 0x2
79
Pankaj Gupta74f7b142020-12-09 14:02:38 +053080#endif /* DCFG_LSCH3_H */