Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 1 | /* |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 2 | * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 5 | */ |
| 6 | #include <arch.h> |
| 7 | #include <asm_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <common/bl_common.h> |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 9 | #include <cortex_a73.h> |
| 10 | #include <cpu_macros.S> |
| 11 | #include <plat_macros.S> |
| 12 | |
| 13 | /* --------------------------------------------- |
| 14 | * Disable L1 data cache |
| 15 | * --------------------------------------------- |
| 16 | */ |
| 17 | func cortex_a73_disable_dcache |
| 18 | mrs x1, sctlr_el3 |
| 19 | bic x1, x1, #SCTLR_C_BIT |
| 20 | msr sctlr_el3, x1 |
| 21 | isb |
| 22 | ret |
| 23 | endfunc cortex_a73_disable_dcache |
| 24 | |
| 25 | /* --------------------------------------------- |
| 26 | * Disable intra-cluster coherency |
| 27 | * --------------------------------------------- |
| 28 | */ |
| 29 | func cortex_a73_disable_smp |
| 30 | mrs x0, CORTEX_A73_CPUECTLR_EL1 |
| 31 | bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT |
| 32 | msr CORTEX_A73_CPUECTLR_EL1, x0 |
| 33 | isb |
| 34 | dsb sy |
| 35 | ret |
| 36 | endfunc cortex_a73_disable_smp |
| 37 | |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 38 | func check_smccc_arch_workaround_3 |
| 39 | mov x0, #ERRATA_APPLIES |
| 40 | ret |
| 41 | endfunc check_smccc_arch_workaround_3 |
| 42 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 43 | workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427 |
Louis Mayencourt | d69722c | 2019-02-27 14:24:16 +0000 | [diff] [blame] | 44 | mrs x1, CORTEX_A73_DIAGNOSTIC_REGISTER |
| 45 | orr x1, x1, #(1 << 12) |
| 46 | msr CORTEX_A73_DIAGNOSTIC_REGISTER, x1 |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 47 | workaround_reset_end cortex_a73, ERRATUM(852427) |
Louis Mayencourt | d69722c | 2019-02-27 14:24:16 +0000 | [diff] [blame] | 48 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 49 | check_erratum_ls cortex_a73, ERRATUM(852427), CPU_REV(0, 0) |
Louis Mayencourt | d69722c | 2019-02-27 14:24:16 +0000 | [diff] [blame] | 50 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 51 | workaround_reset_start cortex_a73, ERRATUM(855423), ERRATA_A73_855423 |
Louis Mayencourt | 4405de6 | 2019-02-21 16:38:16 +0000 | [diff] [blame] | 52 | mrs x1, CORTEX_A73_IMP_DEF_REG2 |
| 53 | orr x1, x1, #(1 << 7) |
| 54 | msr CORTEX_A73_IMP_DEF_REG2, x1 |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 55 | workaround_reset_end cortex_a73, ERRATUM(855423) |
Louis Mayencourt | 4405de6 | 2019-02-21 16:38:16 +0000 | [diff] [blame] | 56 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 57 | check_erratum_ls cortex_a73, ERRATUM(855423), CPU_REV(0, 1) |
Louis Mayencourt | 4405de6 | 2019-02-21 16:38:16 +0000 | [diff] [blame] | 58 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 59 | workaround_reset_start cortex_a73, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 |
| 60 | #if IMAGE_BL31 |
| 61 | adr x0, wa_cve_2017_5715_bpiall_vbar |
| 62 | msr vbar_el3, x0 |
| 63 | #endif /* IMAGE_BL31 */ |
| 64 | workaround_reset_end cortex_a73, CVE(2017, 5715) |
| 65 | |
| 66 | check_erratum_custom_start cortex_a73, CVE(2017, 5715) |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 67 | cpu_check_csv2 x0, 1f |
| 68 | #if WORKAROUND_CVE_2017_5715 |
| 69 | mov x0, #ERRATA_APPLIES |
| 70 | #else |
| 71 | mov x0, #ERRATA_MISSING |
| 72 | #endif |
| 73 | ret |
| 74 | 1: |
| 75 | mov x0, #ERRATA_NOT_APPLIES |
| 76 | ret |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 77 | check_erratum_custom_end cortex_a73, CVE(2017, 5715) |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 78 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 79 | workaround_reset_start cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 |
| 80 | mrs x0, CORTEX_A73_IMP_DEF_REG1 |
| 81 | orr x0, x0, #CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE |
| 82 | msr CORTEX_A73_IMP_DEF_REG1, x0 |
| 83 | workaround_reset_end cortex_a73, CVE(2018, 3639) |
| 84 | |
| 85 | check_erratum_chosen cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 |
| 86 | |
| 87 | workaround_reset_start cortex_a73, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 88 | #if IMAGE_BL31 |
| 89 | /* Skip installing vector table again for CVE_2022_23960 */ |
| 90 | adr x0, wa_cve_2017_5715_bpiall_vbar |
| 91 | mrs x1, vbar_el3 |
| 92 | cmp x0, x1 |
| 93 | b.eq 1f |
| 94 | msr vbar_el3, x0 |
| 95 | 1: |
| 96 | #endif /* IMAGE_BL31 */ |
| 97 | workaround_reset_end cortex_a73, CVE(2022, 23960) |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 98 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 99 | check_erratum_custom_start cortex_a73, CVE(2022, 23960) |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 100 | #if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 101 | cpu_check_csv2 x0, 1f |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 102 | mov x0, #ERRATA_APPLIES |
| 103 | ret |
| 104 | 1: |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 105 | #if WORKAROUND_CVE_2022_23960 |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 106 | mov x0, #ERRATA_APPLIES |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 107 | #else |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 108 | mov x0, #ERRATA_MISSING |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 109 | #endif /* WORKAROUND_CVE_2022_23960 */ |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 110 | ret |
| 111 | #endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ |
| 112 | mov x0, #ERRATA_MISSING |
| 113 | ret |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 114 | check_erratum_custom_end cortex_a73, CVE(2022, 23960) |
Sona Mathew | adc7b32 | 2023-06-19 15:37:09 -0500 | [diff] [blame] | 115 | |
Louis Mayencourt | 4405de6 | 2019-02-21 16:38:16 +0000 | [diff] [blame] | 116 | /* ------------------------------------------------- |
| 117 | * The CPU Ops reset function for Cortex-A73. |
| 118 | * ------------------------------------------------- |
| 119 | */ |
| 120 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 121 | cpu_reset_func_start cortex_a73 |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 122 | /* --------------------------------------------- |
| 123 | * Enable the SMP bit. |
| 124 | * Clobbers : x0 |
| 125 | * --------------------------------------------- |
| 126 | */ |
| 127 | mrs x0, CORTEX_A73_CPUECTLR_EL1 |
| 128 | orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT |
| 129 | msr CORTEX_A73_CPUECTLR_EL1, x0 |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 130 | cpu_reset_func_end cortex_a73 |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 131 | |
| 132 | func cortex_a73_core_pwr_dwn |
| 133 | mov x18, x30 |
| 134 | |
| 135 | /* --------------------------------------------- |
| 136 | * Turn off caches. |
| 137 | * --------------------------------------------- |
| 138 | */ |
| 139 | bl cortex_a73_disable_dcache |
| 140 | |
| 141 | /* --------------------------------------------- |
| 142 | * Flush L1 caches. |
| 143 | * --------------------------------------------- |
| 144 | */ |
| 145 | mov x0, #DCCISW |
| 146 | bl dcsw_op_level1 |
| 147 | |
| 148 | /* --------------------------------------------- |
| 149 | * Come out of intra cluster coherency |
| 150 | * --------------------------------------------- |
| 151 | */ |
| 152 | mov x30, x18 |
| 153 | b cortex_a73_disable_smp |
| 154 | endfunc cortex_a73_core_pwr_dwn |
| 155 | |
| 156 | func cortex_a73_cluster_pwr_dwn |
| 157 | mov x18, x30 |
| 158 | |
| 159 | /* --------------------------------------------- |
| 160 | * Turn off caches. |
| 161 | * --------------------------------------------- |
| 162 | */ |
| 163 | bl cortex_a73_disable_dcache |
| 164 | |
| 165 | /* --------------------------------------------- |
| 166 | * Flush L1 caches. |
| 167 | * --------------------------------------------- |
| 168 | */ |
| 169 | mov x0, #DCCISW |
| 170 | bl dcsw_op_level1 |
| 171 | |
| 172 | /* --------------------------------------------- |
| 173 | * Disable the optional ACP. |
| 174 | * --------------------------------------------- |
| 175 | */ |
| 176 | bl plat_disable_acp |
| 177 | |
| 178 | /* --------------------------------------------- |
| 179 | * Flush L2 caches. |
| 180 | * --------------------------------------------- |
| 181 | */ |
| 182 | mov x0, #DCCISW |
| 183 | bl dcsw_op_level2 |
| 184 | |
| 185 | /* --------------------------------------------- |
| 186 | * Come out of intra cluster coherency |
| 187 | * --------------------------------------------- |
| 188 | */ |
| 189 | mov x30, x18 |
| 190 | b cortex_a73_disable_smp |
| 191 | endfunc cortex_a73_cluster_pwr_dwn |
| 192 | |
Bipin Ravi | caa2e05 | 2022-02-23 23:45:50 -0600 | [diff] [blame] | 193 | |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 194 | errata_report_shim cortex_a73 |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 195 | |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 196 | /* --------------------------------------------- |
| 197 | * This function provides cortex_a73 specific |
| 198 | * register information for crash reporting. |
| 199 | * It needs to return with x6 pointing to |
| 200 | * a list of register names in ascii and |
| 201 | * x8 - x15 having values of registers to be |
| 202 | * reported. |
| 203 | * --------------------------------------------- |
| 204 | */ |
| 205 | .section .rodata.cortex_a73_regs, "aS" |
| 206 | cortex_a73_regs: /* The ascii list of register names to be reported */ |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 207 | .asciz "cpuectlr_el1", "l2merrsr_el1", "" |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 208 | |
| 209 | func cortex_a73_cpu_reg_dump |
| 210 | adr x6, cortex_a73_regs |
| 211 | mrs x8, CORTEX_A73_CPUECTLR_EL1 |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 212 | mrs x9, CORTEX_A73_L2MERRSR_EL1 |
Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 213 | ret |
| 214 | endfunc cortex_a73_cpu_reg_dump |
| 215 | |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 216 | declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \ |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 217 | cortex_a73_reset_func, \ |
Sona Mathew | c1f65de | 2023-06-19 18:52:45 -0500 | [diff] [blame^] | 218 | check_erratum_cortex_a73_5715, \ |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 219 | CPU_NO_EXTRA2_FUNC, \ |
Bipin Ravi | caa2e05 | 2022-02-23 23:45:50 -0600 | [diff] [blame] | 220 | check_smccc_arch_workaround_3, \ |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 221 | cortex_a73_core_pwr_dwn, \ |
| 222 | cortex_a73_cluster_pwr_dwn |