Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 2 | * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __FVP_PWRC_H__ |
| 8 | #define __FVP_PWRC_H__ |
| 9 | |
| 10 | /* FVP Power controller register offset etc */ |
| 11 | #define PPOFFR_OFF 0x0 |
| 12 | #define PPONR_OFF 0x4 |
| 13 | #define PCOFFR_OFF 0x8 |
| 14 | #define PWKUPR_OFF 0xc |
| 15 | #define PSYSR_OFF 0x10 |
| 16 | |
David Cunado | c150312 | 2018-02-16 21:12:58 +0000 | [diff] [blame^] | 17 | #define PWKUPR_WEN (1ULL << 31) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 18 | |
| 19 | #define PSYSR_AFF_L2 (1 << 31) |
| 20 | #define PSYSR_AFF_L1 (1 << 30) |
| 21 | #define PSYSR_AFF_L0 (1 << 29) |
| 22 | #define PSYSR_WEN (1 << 28) |
| 23 | #define PSYSR_PC (1 << 27) |
| 24 | #define PSYSR_PP (1 << 26) |
| 25 | |
| 26 | #define PSYSR_WK_SHIFT 24 |
Soby Mathew | 2ae2319 | 2015-04-30 12:27:41 +0100 | [diff] [blame] | 27 | #define PSYSR_WK_WIDTH 0x2 |
| 28 | #define PSYSR_WK_MASK ((1 << PSYSR_WK_WIDTH) - 1) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 29 | #define PSYSR_WK(x) (x >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK |
| 30 | |
| 31 | #define WKUP_COLD 0x0 |
| 32 | #define WKUP_RESET 0x1 |
| 33 | #define WKUP_PPONR 0x2 |
| 34 | #define WKUP_GICREQ 0x3 |
| 35 | |
| 36 | #define PSYSR_INVALID 0xffffffff |
| 37 | |
| 38 | #ifndef __ASSEMBLY__ |
| 39 | |
| 40 | /******************************************************************************* |
| 41 | * Function & variable prototypes |
| 42 | ******************************************************************************/ |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 43 | void fvp_pwrc_write_pcoffr(u_register_t); |
| 44 | void fvp_pwrc_write_ppoffr(u_register_t); |
| 45 | void fvp_pwrc_write_pponr(u_register_t); |
| 46 | void fvp_pwrc_set_wen(u_register_t); |
| 47 | void fvp_pwrc_clr_wen(u_register_t); |
| 48 | unsigned int fvp_pwrc_read_psysr(u_register_t); |
| 49 | unsigned int fvp_pwrc_get_cpu_wkr(u_register_t); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 50 | |
| 51 | #endif /*__ASSEMBLY__*/ |
| 52 | |
| 53 | #endif /* __FVP_PWRC_H__ */ |