blob: 3a23e4f30a82db0ef868c0b9fe3b3a05f18abcec [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
2 * Copyright (c) 2013, ARM Limited. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __ARCH_H__
32#define __ARCH_H__
33
34#include <bl_common.h>
35
36/*******************************************************************************
37 * MIDR bit definitions
38 ******************************************************************************/
39#define MIDR_PN_MASK 0xfff
40#define MIDR_PN_SHIFT 0x4
41#define MIDR_PN_AEM 0xd0f
42#define MIDR_PN_A57 0xd07
43#define MIDR_PN_A53 0xd03
44
45/*******************************************************************************
46 * MPIDR macros
47 ******************************************************************************/
48#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
49#define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS
50#define MPIDR_AFFINITY_BITS 8
51#define MPIDR_AFFLVL_MASK 0xff
52#define MPIDR_AFF0_SHIFT 0
53#define MPIDR_AFF1_SHIFT 8
54#define MPIDR_AFF2_SHIFT 16
55#define MPIDR_AFF3_SHIFT 32
56#define MPIDR_AFFINITY_MASK 0xff00ffffff
57#define MPIDR_AFFLVL_SHIFT 3
58#define MPIDR_AFFLVL0 0
59#define MPIDR_AFFLVL1 1
60#define MPIDR_AFFLVL2 2
61#define MPIDR_AFFLVL3 3
62/* TODO: Support only the first 3 affinity levels for now */
63#define MPIDR_MAX_AFFLVL 2
64
65/* Constant to highlight the assumption that MPIDR allocation starts from 0 */
66#define FIRST_MPIDR 0
67
68/*******************************************************************************
69 * Implementation defined sysreg encodings
70 ******************************************************************************/
71#define CPUECTLR_EL1 S3_1_C15_C2_1
72
73/*******************************************************************************
74 * System register bit definitions
75 ******************************************************************************/
76/* CLIDR definitions */
77#define LOUIS_SHIFT 21
78#define LOC_SHIFT 24
79#define CLIDR_FIELD_WIDTH 3
80
81/* CSSELR definitions */
82#define LEVEL_SHIFT 1
83
84/* D$ set/way op type defines */
85#define DCISW 0x0
86#define DCCISW 0x1
87#define DCCSW 0x2
88
89/* ID_AA64PFR0_EL1 definitions */
90#define ID_AA64PFR0_EL0_SHIFT 0
91#define ID_AA64PFR0_EL1_SHIFT 4
92#define ID_AA64PFR0_EL2_SHIFT 8
93#define ID_AA64PFR0_EL3_SHIFT 12
94#define ID_AA64PFR0_ELX_MASK 0xf
95
96/* ID_PFR1_EL1 definitions */
97#define ID_PFR1_VIRTEXT_SHIFT 12
98#define ID_PFR1_VIRTEXT_MASK 0xf
99#define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \
100 & ID_PFR1_VIRTEXT_MASK)
101
102/* SCTLR definitions */
103#define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \
104 (1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \
105 (1 << 4))
106
107#define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \
108 (1 << 11))
109#define SCTLR_M_BIT (1 << 0)
110#define SCTLR_A_BIT (1 << 1)
111#define SCTLR_C_BIT (1 << 2)
112#define SCTLR_SA_BIT (1 << 3)
113#define SCTLR_B_BIT (1 << 7)
114#define SCTLR_Z_BIT (1 << 11)
115#define SCTLR_I_BIT (1 << 12)
116#define SCTLR_WXN_BIT (1 << 19)
117#define SCTLR_EXCEPTION_BITS (0x3 << 6)
118#define SCTLR_EE_BIT (1 << 25)
119
120/* CPUECTLR definitions */
121#define CPUECTLR_SMP_BIT (1 << 6)
122
123/* CPACR_El1 definitions */
124#define CPACR_EL1_FPEN(x) (x << 20)
125#define CPACR_EL1_FP_TRAP_EL0 0x1
126#define CPACR_EL1_FP_TRAP_ALL 0x2
127#define CPACR_EL1_FP_TRAP_NONE 0x3
128
129/* SCR definitions */
130#define SCR_RES1_BITS ((1 << 4) | (1 << 5))
131#define SCR_TWE_BIT (1 << 13)
132#define SCR_TWI_BIT (1 << 12)
133#define SCR_ST_BIT (1 << 11)
134#define SCR_RW_BIT (1 << 10)
135#define SCR_SIF_BIT (1 << 9)
136#define SCR_HCE_BIT (1 << 8)
137#define SCR_SMD_BIT (1 << 7)
138#define SCR_EA_BIT (1 << 3)
139#define SCR_FIQ_BIT (1 << 2)
140#define SCR_IRQ_BIT (1 << 1)
141#define SCR_NS_BIT (1 << 0)
142
143/* HCR definitions */
144#define HCR_RW_BIT (1ull << 31)
145#define HCR_AMO_BIT (1 << 5)
146#define HCR_IMO_BIT (1 << 4)
147#define HCR_FMO_BIT (1 << 3)
148
149/* CNTHCTL_EL2 definitions */
150#define EL1PCEN_BIT (1 << 1)
151#define EL1PCTEN_BIT (1 << 0)
152
153/* CNTKCTL_EL1 definitions */
154#define EL0PTEN_BIT (1 << 9)
155#define EL0VTEN_BIT (1 << 8)
156#define EL0PCTEN_BIT (1 << 0)
157#define EL0VCTEN_BIT (1 << 1)
158
159/* CPTR_EL3 definitions */
160#define TCPAC_BIT (1ull << 31)
161#define TFP_BIT (1 << 10)
162
163/* CPSR/SPSR definitions */
164#define DAIF_FIQ_BIT (1 << 0)
165#define DAIF_IRQ_BIT (1 << 1)
166#define DAIF_ABT_BIT (1 << 2)
167#define DAIF_DBG_BIT (1 << 3)
168#define PSR_DAIF_SHIFT 0x6
169
170/*
171 * TCR defintions
172 */
173#define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23))
174
175#define TCR_T0SZ_4GB 32
176
177#define TCR_RGN_INNER_NC (0x0 << 8)
178#define TCR_RGN_INNER_WBA (0x1 << 8)
179#define TCR_RGN_INNER_WT (0x2 << 8)
180#define TCR_RGN_INNER_WBNA (0x3 << 8)
181
182#define TCR_RGN_OUTER_NC (0x0 << 10)
183#define TCR_RGN_OUTER_WBA (0x1 << 10)
184#define TCR_RGN_OUTER_WT (0x2 << 10)
185#define TCR_RGN_OUTER_WBNA (0x3 << 10)
186
187#define TCR_SH_NON_SHAREABLE (0x0 << 12)
188#define TCR_SH_OUTER_SHAREABLE (0x2 << 12)
189#define TCR_SH_INNER_SHAREABLE (0x3 << 12)
190
191#define MODE_RW_64 0x0
192#define MODE_RW_32 0x1
193#define MODE_SP_EL0 0x0
194#define MODE_SP_ELX 0x1
195#define MODE_EL3 0x3
196#define MODE_EL2 0x2
197#define MODE_EL1 0x1
198#define MODE_EL0 0x0
199
200#define MODE_RW_SHIFT 0x4
201#define MODE_EL_SHIFT 0x2
202#define MODE_SP_SHIFT 0x0
203
204#define GET_RW(mode) ((mode >> MODE_RW_SHIFT) & 0x1)
205#define GET_EL(mode) ((mode >> MODE_EL_SHIFT) & 0x3)
206#define GET_SP(mode) ((mode >> MODE_SP_SHIFT) & 0x1)
207#define PSR_MODE(rw, el, sp) (rw << MODE_RW_SHIFT | el << MODE_EL_SHIFT \
208 | sp << MODE_SP_SHIFT)
209
210#define SPSR32_EE_BIT (1 << 9)
211#define SPSR32_T_BIT (1 << 5)
212
213#define AARCH32_MODE_SVC 0x13
214#define AARCH32_MODE_HYP 0x1a
215
216/* Miscellaneous MMU related constants */
217#define NUM_2MB_IN_GB (1 << 9)
218#define NUM_4K_IN_2MB (1 << 9)
219
220#define TWO_MB_SHIFT 21
221#define ONE_GB_SHIFT 30
222#define FOUR_KB_SHIFT 12
223
224#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT)
225#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT)
226#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT)
227
228#define INVALID_DESC 0x0
229#define BLOCK_DESC 0x1
230#define TABLE_DESC 0x3
231
232#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT
233#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT
234#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT
235
236#define LEVEL1 1
237#define LEVEL2 2
238#define LEVEL3 3
239
240#define XN (1ull << 2)
241#define PXN (1ull << 1)
242#define CONT_HINT (1ull << 0)
243
244#define UPPER_ATTRS(x) (x & 0x7) << 52
245#define NON_GLOBAL (1 << 9)
246#define ACCESS_FLAG (1 << 8)
247#define NSH (0x0 << 6)
248#define OSH (0x2 << 6)
249#define ISH (0x3 << 6)
250
251/*
252 * AP[1] bit is ignored by hardware and is
253 * treated as if it is One in EL2/EL3
254 */
255#define AP_RO (0x1 << 5)
256#define AP_RW (0x0 << 5)
257
258#define NS (0x1 << 3)
259#define ATTR_SO_INDEX 0x2
260#define ATTR_DEVICE_INDEX 0x1
261#define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0
262#define LOWER_ATTRS(x) (((x) & 0xfff) << 2)
263#define ATTR_SO (0x0)
264#define ATTR_DEVICE (0x4)
265#define ATTR_IWBWA_OWBWA_NTR (0xff)
266#define MAIR_ATTR_SET(attr, index) (attr << (index << 3))
267
268/* Exception Syndrome register bits and bobs */
269#define ESR_EC_SHIFT 26
270#define ESR_EC_MASK 0x3f
271#define ESR_EC_LENGTH 6
272#define EC_UNKNOWN 0x0
273#define EC_WFE_WFI 0x1
274#define EC_AARCH32_CP15_MRC_MCR 0x3
275#define EC_AARCH32_CP15_MRRC_MCRR 0x4
276#define EC_AARCH32_CP14_MRC_MCR 0x5
277#define EC_AARCH32_CP14_LDC_STC 0x6
278#define EC_FP_SIMD 0x7
279#define EC_AARCH32_CP10_MRC 0x8
280#define EC_AARCH32_CP14_MRRC_MCRR 0xc
281#define EC_ILLEGAL 0xe
282#define EC_AARCH32_SVC 0x11
283#define EC_AARCH32_HVC 0x12
284#define EC_AARCH32_SMC 0x13
285#define EC_AARCH64_SVC 0x15
286#define EC_AARCH64_HVC 0x16
287#define EC_AARCH64_SMC 0x17
288#define EC_AARCH64_SYS 0x18
289#define EC_IABORT_LOWER_EL 0x20
290#define EC_IABORT_CUR_EL 0x21
291#define EC_PC_ALIGN 0x22
292#define EC_DABORT_LOWER_EL 0x24
293#define EC_DABORT_CUR_EL 0x25
294#define EC_SP_ALIGN 0x26
295#define EC_AARCH32_FP 0x28
296#define EC_AARCH64_FP 0x2c
297#define EC_SERROR 0x2f
298
299#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK
300
301#ifndef __ASSEMBLY__
302
303/*******************************************************************************
304 * Function prototypes
305 ******************************************************************************/
306
307extern void early_exceptions(void);
308extern void runtime_exceptions(void);
309extern void bl1_arch_setup(void);
310extern void bl2_arch_setup(void);
311extern void bl31_arch_setup(void);
312
313#endif /*__ASSEMBLY__*/
314
315#endif /* __ARCH_H__ */