Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013, ARM Limited. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <stdio.h> |
| 32 | #include <string.h> |
| 33 | #include <assert.h> |
| 34 | #include <arch_helpers.h> |
| 35 | #include <console.h> |
| 36 | #include <platform.h> |
| 37 | #include <psci.h> |
| 38 | #include <psci_private.h> |
| 39 | |
| 40 | typedef int (*afflvl_suspend_handler)(unsigned long, |
| 41 | aff_map_node *, |
| 42 | unsigned long, |
| 43 | unsigned long, |
| 44 | unsigned int); |
| 45 | |
| 46 | /******************************************************************************* |
| 47 | * The next three functions implement a handler for each supported affinity |
| 48 | * level which is called when that affinity level is about to be suspended. |
| 49 | ******************************************************************************/ |
| 50 | static int psci_afflvl0_suspend(unsigned long mpidr, |
| 51 | aff_map_node *cpu_node, |
| 52 | unsigned long ns_entrypoint, |
| 53 | unsigned long context_id, |
| 54 | unsigned int power_state) |
| 55 | { |
| 56 | unsigned int index, plat_state; |
| 57 | unsigned long psci_entrypoint, sctlr = read_sctlr(); |
| 58 | int rc = PSCI_E_SUCCESS; |
| 59 | |
| 60 | /* Sanity check to safeguard against data corruption */ |
| 61 | assert(cpu_node->level == MPIDR_AFFLVL0); |
| 62 | |
| 63 | /* |
| 64 | * Generic management: Store the re-entry information for the |
| 65 | * non-secure world |
| 66 | */ |
| 67 | index = cpu_node->data; |
| 68 | rc = psci_set_ns_entry_info(index, ns_entrypoint, context_id); |
| 69 | if (rc != PSCI_E_SUCCESS) |
| 70 | return rc; |
| 71 | |
| 72 | /* |
| 73 | * Arch. management: Save the secure context, flush the |
| 74 | * L1 caches and exit intra-cluster coherency et al |
| 75 | */ |
| 76 | psci_secure_context[index].sctlr = read_sctlr(); |
| 77 | psci_secure_context[index].scr = read_scr(); |
| 78 | psci_secure_context[index].cptr = read_cptr(); |
| 79 | psci_secure_context[index].cpacr = read_cpacr(); |
| 80 | psci_secure_context[index].cntfrq = read_cntfrq_el0(); |
| 81 | psci_secure_context[index].mair = read_mair(); |
| 82 | psci_secure_context[index].tcr = read_tcr(); |
| 83 | psci_secure_context[index].ttbr = read_ttbr0(); |
| 84 | psci_secure_context[index].vbar = read_vbar(); |
| 85 | |
| 86 | /* Set the secure world (EL3) re-entry point after BL1 */ |
| 87 | psci_entrypoint = (unsigned long) psci_aff_suspend_finish_entry; |
| 88 | |
| 89 | /* |
| 90 | * Arch. management. Perform the necessary steps to flush all |
| 91 | * cpu caches. |
| 92 | * |
| 93 | * TODO: This power down sequence varies across cpus so it needs to be |
| 94 | * abstracted out on the basis of the MIDR like in cpu_reset_handler(). |
| 95 | * Do the bare minimal for the time being. Fix this before porting to |
| 96 | * Cortex models. |
| 97 | */ |
| 98 | sctlr &= ~SCTLR_C_BIT; |
| 99 | write_sctlr(sctlr); |
| 100 | |
| 101 | /* |
| 102 | * CAUTION: This flush to the level of unification makes an assumption |
| 103 | * about the cache hierarchy at affinity level 0 (cpu) in the platform. |
| 104 | * Ideally the platform should tell psci which levels to flush to exit |
| 105 | * coherency. |
| 106 | */ |
| 107 | dcsw_op_louis(DCCISW); |
| 108 | |
| 109 | /* |
| 110 | * Plat. management: Allow the platform to perform the |
| 111 | * necessary actions to turn off this cpu e.g. set the |
| 112 | * platform defined mailbox with the psci entrypoint, |
| 113 | * program the power controller etc. |
| 114 | */ |
| 115 | if (psci_plat_pm_ops->affinst_suspend) { |
| 116 | plat_state = psci_get_aff_phys_state(cpu_node); |
| 117 | rc = psci_plat_pm_ops->affinst_suspend(mpidr, |
| 118 | psci_entrypoint, |
| 119 | ns_entrypoint, |
| 120 | cpu_node->level, |
| 121 | plat_state); |
| 122 | } |
| 123 | |
| 124 | return rc; |
| 125 | } |
| 126 | |
| 127 | static int psci_afflvl1_suspend(unsigned long mpidr, |
| 128 | aff_map_node *cluster_node, |
| 129 | unsigned long ns_entrypoint, |
| 130 | unsigned long context_id, |
| 131 | unsigned int power_state) |
| 132 | { |
| 133 | int rc = PSCI_E_SUCCESS; |
| 134 | unsigned int plat_state; |
| 135 | unsigned long psci_entrypoint; |
| 136 | |
| 137 | /* Sanity check the cluster level */ |
| 138 | assert(cluster_node->level == MPIDR_AFFLVL1); |
| 139 | |
| 140 | /* |
| 141 | * Keep the physical state of this cluster handy to decide |
| 142 | * what action needs to be taken |
| 143 | */ |
| 144 | plat_state = psci_get_aff_phys_state(cluster_node); |
| 145 | |
| 146 | /* |
| 147 | * Arch. management: Flush all levels of caches to PoC if the |
| 148 | * cluster is to be shutdown |
| 149 | */ |
| 150 | if (plat_state == PSCI_STATE_OFF) |
| 151 | dcsw_op_all(DCCISW); |
| 152 | |
| 153 | /* |
| 154 | * Plat. Management. Allow the platform to do it's cluster |
| 155 | * specific bookeeping e.g. turn off interconnect coherency, |
| 156 | * program the power controller etc. |
| 157 | */ |
| 158 | if (psci_plat_pm_ops->affinst_suspend) { |
| 159 | |
| 160 | /* |
| 161 | * Sending the psci entrypoint is currently redundant |
| 162 | * beyond affinity level 0 but one never knows what a |
| 163 | * platform might do. Also it allows us to keep the |
| 164 | * platform handler prototype the same. |
| 165 | */ |
| 166 | psci_entrypoint = (unsigned long) psci_aff_suspend_finish_entry; |
| 167 | |
| 168 | rc = psci_plat_pm_ops->affinst_suspend(mpidr, |
| 169 | psci_entrypoint, |
| 170 | ns_entrypoint, |
| 171 | cluster_node->level, |
| 172 | plat_state); |
| 173 | } |
| 174 | |
| 175 | return rc; |
| 176 | } |
| 177 | |
| 178 | |
| 179 | static int psci_afflvl2_suspend(unsigned long mpidr, |
| 180 | aff_map_node *system_node, |
| 181 | unsigned long ns_entrypoint, |
| 182 | unsigned long context_id, |
| 183 | unsigned int power_state) |
| 184 | { |
| 185 | int rc = PSCI_E_SUCCESS; |
| 186 | unsigned int plat_state; |
| 187 | unsigned long psci_entrypoint; |
| 188 | |
| 189 | /* Cannot go beyond this */ |
| 190 | assert(system_node->level == MPIDR_AFFLVL2); |
| 191 | |
| 192 | /* |
| 193 | * Keep the physical state of the system handy to decide what |
| 194 | * action needs to be taken |
| 195 | */ |
| 196 | plat_state = psci_get_aff_phys_state(system_node); |
| 197 | |
| 198 | /* |
| 199 | * Plat. Management : Allow the platform to do it's bookeeping |
| 200 | * at this affinity level |
| 201 | */ |
| 202 | if (psci_plat_pm_ops->affinst_suspend) { |
| 203 | |
| 204 | /* |
| 205 | * Sending the psci entrypoint is currently redundant |
| 206 | * beyond affinity level 0 but one never knows what a |
| 207 | * platform might do. Also it allows us to keep the |
| 208 | * platform handler prototype the same. |
| 209 | */ |
| 210 | psci_entrypoint = (unsigned long) psci_aff_suspend_finish_entry; |
| 211 | |
| 212 | rc = psci_plat_pm_ops->affinst_suspend(mpidr, |
| 213 | psci_entrypoint, |
| 214 | ns_entrypoint, |
| 215 | system_node->level, |
| 216 | plat_state); |
| 217 | } |
| 218 | |
| 219 | return rc; |
| 220 | } |
| 221 | |
| 222 | static const afflvl_suspend_handler psci_afflvl_suspend_handlers[] = { |
| 223 | psci_afflvl0_suspend, |
| 224 | psci_afflvl1_suspend, |
| 225 | psci_afflvl2_suspend, |
| 226 | }; |
| 227 | |
| 228 | /******************************************************************************* |
| 229 | * This function implements the core of the processing required to suspend a cpu |
| 230 | * It'S assumed that along with suspending the cpu, higher affinity levels will |
| 231 | * be suspended as far as possible. Suspending a cpu is equivalent to physically |
| 232 | * powering it down, but the cpu is still available to the OS for scheduling. |
| 233 | * We first need to determine the new state off all the affinity instances in |
| 234 | * the mpidr corresponding to the target cpu. Action will be taken on the basis |
| 235 | * of this new state. To do the state change we first need to acquire the locks |
| 236 | * for all the implemented affinity level to be able to snapshot the system |
| 237 | * state. Then we need to start suspending affinity levels from the lowest to |
| 238 | * the highest (e.g. a cpu needs to be suspended before a cluster can be). To |
| 239 | * achieve this flow, we start acquiring the locks from the highest to the |
| 240 | * lowest affinity level. Once we reach affinity level 0, we do the state change |
| 241 | * followed by the actions corresponding to the new state for affinity level 0. |
| 242 | * Actions as per the updated state for higher affinity levels are performed as |
| 243 | * we unwind back to highest affinity level. |
| 244 | ******************************************************************************/ |
| 245 | int psci_afflvl_suspend(unsigned long mpidr, |
| 246 | unsigned long entrypoint, |
| 247 | unsigned long context_id, |
| 248 | unsigned int power_state, |
| 249 | int cur_afflvl, |
| 250 | int tgt_afflvl) |
| 251 | { |
| 252 | int rc = PSCI_E_SUCCESS, level; |
| 253 | unsigned int prev_state, next_state; |
| 254 | aff_map_node *aff_node; |
| 255 | |
| 256 | mpidr &= MPIDR_AFFINITY_MASK; |
| 257 | |
| 258 | /* |
| 259 | * Some affinity instances at levels between the current and |
| 260 | * target levels could be absent in the mpidr. Skip them and |
| 261 | * start from the first present instance. |
| 262 | */ |
| 263 | level = psci_get_first_present_afflvl(mpidr, |
| 264 | cur_afflvl, |
| 265 | tgt_afflvl, |
| 266 | &aff_node); |
| 267 | |
| 268 | /* |
| 269 | * Return if there are no more affinity instances beyond this |
| 270 | * level to process. Else ensure that the returned affinity |
| 271 | * node makes sense. |
| 272 | */ |
| 273 | if (aff_node == NULL) |
| 274 | return rc; |
| 275 | |
| 276 | assert(level == aff_node->level); |
| 277 | |
| 278 | /* |
| 279 | * This function acquires the lock corresponding to each |
| 280 | * affinity level so that state management can be done safely. |
| 281 | */ |
| 282 | bakery_lock_get(mpidr, &aff_node->lock); |
| 283 | |
| 284 | /* Keep the old state and the next one handy */ |
| 285 | prev_state = psci_get_state(aff_node->state); |
| 286 | next_state = PSCI_STATE_SUSPEND; |
| 287 | |
| 288 | /* |
| 289 | * We start from the highest affinity level and work our way |
| 290 | * downwards to the lowest i.e. MPIDR_AFFLVL0. |
| 291 | */ |
| 292 | if (aff_node->level == tgt_afflvl) { |
| 293 | psci_change_state(mpidr, |
| 294 | tgt_afflvl, |
| 295 | get_max_afflvl(), |
| 296 | next_state); |
| 297 | } else { |
| 298 | rc = psci_afflvl_suspend(mpidr, |
| 299 | entrypoint, |
| 300 | context_id, |
| 301 | power_state, |
| 302 | level - 1, |
| 303 | tgt_afflvl); |
| 304 | if (rc != PSCI_E_SUCCESS) { |
| 305 | psci_set_state(aff_node->state, prev_state); |
| 306 | goto exit; |
| 307 | } |
| 308 | } |
| 309 | |
| 310 | /* |
| 311 | * Perform generic, architecture and platform specific |
| 312 | * handling |
| 313 | */ |
| 314 | rc = psci_afflvl_suspend_handlers[level](mpidr, |
| 315 | aff_node, |
| 316 | entrypoint, |
| 317 | context_id, |
| 318 | power_state); |
| 319 | if (rc != PSCI_E_SUCCESS) { |
| 320 | psci_set_state(aff_node->state, prev_state); |
| 321 | goto exit; |
| 322 | } |
| 323 | |
| 324 | /* |
| 325 | * If all has gone as per plan then this cpu should be |
| 326 | * marked as OFF |
| 327 | */ |
| 328 | if (level == MPIDR_AFFLVL0) { |
| 329 | next_state = psci_get_state(aff_node->state); |
| 330 | assert(next_state == PSCI_STATE_SUSPEND); |
| 331 | } |
| 332 | |
| 333 | exit: |
| 334 | bakery_lock_release(mpidr, &aff_node->lock); |
| 335 | return rc; |
| 336 | } |
| 337 | |
| 338 | /******************************************************************************* |
| 339 | * The following functions finish an earlier affinity suspend request. They |
| 340 | * are called by the common finisher routine in psci_common.c. |
| 341 | ******************************************************************************/ |
| 342 | static unsigned int psci_afflvl0_suspend_finish(unsigned long mpidr, |
| 343 | aff_map_node *cpu_node, |
| 344 | unsigned int prev_state) |
| 345 | { |
| 346 | unsigned int index, plat_state, rc = 0; |
| 347 | |
| 348 | assert(cpu_node->level == MPIDR_AFFLVL0); |
| 349 | |
| 350 | /* |
| 351 | * Plat. management: Perform the platform specific actions |
| 352 | * before we change the state of the cpu e.g. enabling the |
| 353 | * gic or zeroing the mailbox register. If anything goes |
| 354 | * wrong then assert as there is no way to recover from this |
| 355 | * situation. |
| 356 | */ |
| 357 | if (psci_plat_pm_ops->affinst_suspend_finish) { |
| 358 | plat_state = psci_get_phys_state(prev_state); |
| 359 | rc = psci_plat_pm_ops->affinst_suspend_finish(mpidr, |
| 360 | cpu_node->level, |
| 361 | plat_state); |
| 362 | assert(rc == PSCI_E_SUCCESS); |
| 363 | } |
| 364 | |
| 365 | /* Get the index for restoring the re-entry information */ |
| 366 | index = cpu_node->data; |
| 367 | |
| 368 | /* |
| 369 | * Arch. management: Restore the stashed secure architectural |
| 370 | * context in the right order. |
| 371 | */ |
| 372 | write_vbar(psci_secure_context[index].vbar); |
| 373 | write_mair(psci_secure_context[index].mair); |
| 374 | write_tcr(psci_secure_context[index].tcr); |
| 375 | write_ttbr0(psci_secure_context[index].ttbr); |
| 376 | write_sctlr(psci_secure_context[index].sctlr); |
| 377 | |
| 378 | /* MMU and coherency should be enabled by now */ |
| 379 | write_scr(psci_secure_context[index].scr); |
| 380 | write_cptr(psci_secure_context[index].cptr); |
| 381 | write_cpacr(psci_secure_context[index].cpacr); |
| 382 | write_cntfrq_el0(psci_secure_context[index].cntfrq); |
| 383 | |
| 384 | /* |
| 385 | * Generic management: Now we just need to retrieve the |
| 386 | * information that we had stashed away during the suspend |
| 387 | * call to set this cpu on it's way. |
| 388 | */ |
| 389 | rc = psci_get_ns_entry_info(index); |
| 390 | |
| 391 | /* Clean caches before re-entering normal world */ |
| 392 | dcsw_op_louis(DCCSW); |
| 393 | |
| 394 | return rc; |
| 395 | } |
| 396 | |
| 397 | static unsigned int psci_afflvl1_suspend_finish(unsigned long mpidr, |
| 398 | aff_map_node *cluster_node, |
| 399 | unsigned int prev_state) |
| 400 | { |
| 401 | unsigned int rc = 0; |
| 402 | unsigned int plat_state; |
| 403 | |
| 404 | assert(cluster_node->level == MPIDR_AFFLVL1); |
| 405 | |
| 406 | /* |
| 407 | * Plat. management: Perform the platform specific actions |
| 408 | * as per the old state of the cluster e.g. enabling |
| 409 | * coherency at the interconnect depends upon the state with |
| 410 | * which this cluster was powered up. If anything goes wrong |
| 411 | * then assert as there is no way to recover from this |
| 412 | * situation. |
| 413 | */ |
| 414 | if (psci_plat_pm_ops->affinst_suspend_finish) { |
| 415 | plat_state = psci_get_phys_state(prev_state); |
| 416 | rc = psci_plat_pm_ops->affinst_suspend_finish(mpidr, |
| 417 | cluster_node->level, |
| 418 | plat_state); |
| 419 | assert(rc == PSCI_E_SUCCESS); |
| 420 | } |
| 421 | |
| 422 | return rc; |
| 423 | } |
| 424 | |
| 425 | |
| 426 | static unsigned int psci_afflvl2_suspend_finish(unsigned long mpidr, |
| 427 | aff_map_node *system_node, |
| 428 | unsigned int target_afflvl) |
| 429 | { |
| 430 | int rc = PSCI_E_SUCCESS; |
| 431 | unsigned int plat_state; |
| 432 | |
| 433 | /* Cannot go beyond this affinity level */ |
| 434 | assert(system_node->level == MPIDR_AFFLVL2); |
| 435 | |
| 436 | /* |
| 437 | * Currently, there are no architectural actions to perform |
| 438 | * at the system level. |
| 439 | */ |
| 440 | |
| 441 | /* |
| 442 | * Plat. management: Perform the platform specific actions |
| 443 | * as per the old state of the cluster e.g. enabling |
| 444 | * coherency at the interconnect depends upon the state with |
| 445 | * which this cluster was powered up. If anything goes wrong |
| 446 | * then assert as there is no way to recover from this |
| 447 | * situation. |
| 448 | */ |
| 449 | if (psci_plat_pm_ops->affinst_suspend_finish) { |
| 450 | plat_state = psci_get_phys_state(system_node->state); |
| 451 | rc = psci_plat_pm_ops->affinst_suspend_finish(mpidr, |
| 452 | system_node->level, |
| 453 | plat_state); |
| 454 | assert(rc == PSCI_E_SUCCESS); |
| 455 | } |
| 456 | |
| 457 | return rc; |
| 458 | } |
| 459 | |
| 460 | const afflvl_power_on_finisher psci_afflvl_suspend_finishers[] = { |
| 461 | psci_afflvl0_suspend_finish, |
| 462 | psci_afflvl1_suspend_finish, |
| 463 | psci_afflvl2_suspend_finish, |
| 464 | }; |
| 465 | |