blob: b4dbe5f4b0f81214c963ffa8da5c9052427cb821 [file] [log] [blame]
Muhammad Hadi Asyrafi Abdul Halimc0d4d932019-03-19 17:59:06 +08001/*
2 * Copyright (c) 2019, Intel Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/debug.h>
8#include <lib/mmio.h>
9#include <platform_def.h>
10
11#include "watchdog.h"
12
13
14/* Reset watchdog timer */
15void watchdog_sw_rst(void)
16{
17 mmio_write_32(WDT_CRR, WDT_SW_RST);
18}
19
20/* Print component information */
21void watchdog_info(void)
22{
23 INFO("Component Type : %x\r\n", mmio_read_32(WDT_COMP_VERSION));
24 INFO("Component Version : %x\r\n", mmio_read_32(WDT_COMP_TYPE));
25}
26
27/* Check watchdog current status */
28void watchdog_status(void)
29{
30 if (mmio_read_32(WDT_CR) & 1) {
31 INFO("Watchdog Timer in currently enabled\n");
32 INFO("Current Counter : 0x%x\r\n", mmio_read_32(WDT_CCVR));
33 } else {
34 INFO("Watchdog Timer in currently disabled\n");
35 }
36}
37
38/* Initialize & enable watchdog */
39void watchdog_init(int watchdog_clk)
40{
41 uint8_t cycles_i = 0;
42 uint32_t wdt_cycles = WDT_MIN_CYCLES;
43 uint32_t top_init_cycles = WDT_PERIOD * watchdog_clk;
44
45 while ((cycles_i < 15) && (wdt_cycles < top_init_cycles)) {
46 wdt_cycles = (wdt_cycles << 1);
47 cycles_i++;
48 }
49
50 mmio_write_32(WDT_TORR, (cycles_i << 4) | cycles_i);
51
52 watchdog_enable();
53}
54
55void watchdog_enable(void)
56{
57 mmio_write_32(WDT_CR, WDT_CR_RMOD|WDT_CR_EN);
58}