Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Roberto Vargas | 2b36b15 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 7 | #include <platform_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
| 9 | #include <drivers/arm/nic_400.h> |
| 10 | #include <lib/mmio.h> |
| 11 | |
| 12 | #include <board_css_def.h> |
Roberto Vargas | 2b36b15 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 13 | #include <soc_css.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 14 | #include <soc_css_def.h> |
| 15 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 16 | void soc_css_init_nic400(void) |
| 17 | { |
| 18 | /* |
| 19 | * NIC-400 Access Control Initialization |
| 20 | * |
| 21 | * Define access privileges by setting each corresponding bit to: |
| 22 | * 0 = Secure access only |
| 23 | * 1 = Non-secure access allowed |
| 24 | */ |
| 25 | |
| 26 | /* |
| 27 | * Allow non-secure access to some SOC regions, excluding UART1, which |
Alexei Fedorov | e9ab905 | 2017-05-25 15:57:18 +0100 | [diff] [blame] | 28 | * remains secure (unless CSS_NON_SECURE_UART is set). |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 29 | * Note: This is the NIC-400 device on the SOC |
| 30 | */ |
| 31 | mmio_write_32(SOC_CSS_NIC400_BASE + |
| 32 | NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_EHCI), ~0); |
| 33 | mmio_write_32(SOC_CSS_NIC400_BASE + |
| 34 | NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_TLX_MASTER), ~0); |
| 35 | mmio_write_32(SOC_CSS_NIC400_BASE + |
| 36 | NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_OHCI), ~0); |
| 37 | mmio_write_32(SOC_CSS_NIC400_BASE + |
| 38 | NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_PL354_SMC), ~0); |
| 39 | mmio_write_32(SOC_CSS_NIC400_BASE + |
| 40 | NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_APB4_BRIDGE), ~0); |
Alexei Fedorov | e9ab905 | 2017-05-25 15:57:18 +0100 | [diff] [blame] | 41 | #if CSS_NON_SECURE_UART |
| 42 | /* Configure UART for non-secure access */ |
| 43 | mmio_write_32(SOC_CSS_NIC400_BASE + |
| 44 | NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE), ~0); |
| 45 | #else |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 46 | mmio_write_32(SOC_CSS_NIC400_BASE + |
| 47 | NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE), |
| 48 | ~SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1); |
Alexei Fedorov | e9ab905 | 2017-05-25 15:57:18 +0100 | [diff] [blame] | 49 | #endif /* CSS_NON_SECURE_UART */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 50 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 51 | } |
| 52 | |
| 53 | |
| 54 | #define PCIE_SECURE_REG 0x3000 |
| 55 | /* Mask uses REG and MEM access bits */ |
| 56 | #define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) |
| 57 | |
| 58 | void soc_css_init_pcie(void) |
| 59 | { |
| 60 | #if !PLAT_juno |
| 61 | /* |
| 62 | * Do not initialize PCIe in emulator environment. |
| 63 | * Platform ID register not supported on Juno |
| 64 | */ |
| 65 | if (BOARD_CSS_GET_PLAT_TYPE(BOARD_CSS_PLAT_ID_REG_ADDR) == |
| 66 | BOARD_CSS_PLAT_TYPE_EMULATOR) |
| 67 | return; |
| 68 | #endif /* PLAT_juno */ |
| 69 | |
| 70 | /* |
| 71 | * PCIE Root Complex Security settings to enable non-secure |
| 72 | * access to config registers. |
| 73 | */ |
| 74 | mmio_write_32(SOC_CSS_PCIE_CONTROL_BASE + PCIE_SECURE_REG, |
| 75 | PCIE_SEC_ACCESS_MASK); |
| 76 | } |