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Vikram Kanigiri510d87b2016-01-29 12:32:58 +00001/*
Summer Qin5ce394c2018-03-12 11:28:26 +08002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Vikram Kanigiri510d87b2016-01-29 12:32:58 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Vikram Kanigiri510d87b2016-01-29 12:32:58 +00005 */
6
Vikram Kanigiri510d87b2016-01-29 12:32:58 +00007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Vikram Kanigiri510d87b2016-01-29 12:32:58 +00009#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <common/debug.h>
12#include <drivers/arm/tzc_dmc500.h>
13
14#include <arm_def.h>
15#include <plat_arm.h>
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000016
17/*******************************************************************************
18 * Initialize the DMC500-TrustZone Controller for ARM standard platforms.
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000019 * When booting an EL3 payload, this is simplified: we configure region 0 with
20 * secure access only and do not enable any other region.
21 ******************************************************************************/
Summer Qin5ce394c2018-03-12 11:28:26 +080022void arm_tzc_dmc500_setup(tzc_dmc500_driver_data_t *plat_driver_data,
23 const arm_tzc_regions_info_t *tzc_regions)
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000024{
Summer Qin5ce394c2018-03-12 11:28:26 +080025#ifndef EL3_PAYLOAD_BASE
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010026 unsigned int region_index = 1U;
Summer Qin5ce394c2018-03-12 11:28:26 +080027 const arm_tzc_regions_info_t *p;
28 const arm_tzc_regions_info_t init_tzc_regions[] = {
29 ARM_TZC_REGIONS_DEF,
30 {0}
31 };
32#endif
33
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000034 assert(plat_driver_data);
35
36 INFO("Configuring DMC-500 TZ Settings\n");
37
38 tzc_dmc500_driver_init(plat_driver_data);
39
40#ifndef EL3_PAYLOAD_BASE
Summer Qin5ce394c2018-03-12 11:28:26 +080041 if (tzc_regions == NULL)
42 p = init_tzc_regions;
43 else
44 p = tzc_regions;
45
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000046 /* Region 0 set to no access by default */
47 tzc_dmc500_configure_region0(TZC_REGION_S_NONE, 0);
48
Summer Qin5ce394c2018-03-12 11:28:26 +080049 /* Rest Regions set according to tzc_regions array */
50 for (; p->base != 0ULL; p++) {
51 tzc_dmc500_configure_region(region_index, p->base, p->end,
52 p->sec_attr, p->nsaid_permissions);
53 region_index++;
54 }
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000055
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010056 INFO("Total %u regions set.\n", region_index);
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000057
Vikram Kanigiri510d87b2016-01-29 12:32:58 +000058#else
59 /* Allow secure access only to DRAM for EL3 payloads */
60 tzc_dmc500_configure_region0(TZC_REGION_S_RDWR, 0);
61#endif
62 /*
63 * Raise an exception if a NS device tries to access secure memory
64 * TODO: Add interrupt handling support.
65 */
66 tzc_dmc500_set_action(TZC_ACTION_RV_LOWERR);
67
68 /*
69 * Flush the configuration settings to have an affect. Validate
70 * flush by checking FILTER_EN is set on region 1 attributes
71 * register.
72 */
73 tzc_dmc500_config_complete();
74
75 /*
76 * Wait for the flush to complete.
77 * TODO: Have a timeout for this loop
78 */
79 while (tzc_dmc500_verify_complete())
80 ;
81}