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git01.mediatek.com / filogic / atf / c0415c6335f2ba2d3345b0cc710ef3748d23fd86 / . / drivers / staging / renesas / rcar / ddr / ddr_a / ddr_init_e3.c
blob: 74677f64c3aa50cb1125801cd8b2b1d19443c8c0 [file] [log] [blame]
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1/*
2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]7#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]8
9#include <common/debug.h>
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]10
11#include "boot_init_dram_regdef_e3.h"
12#include "ddr_init_e3.h"
13
14#include "../dram_sub_func.h"
15
16/* rev.0.04 add variables */
17/*******************************************************************************
18 * variables
19 ******************************************************************************/
20uint32_t ddrBackup;
21
22/* rev.0.03 add Prototypes */
23/*******************************************************************************
24 * Prototypes
25 ******************************************************************************/
26/* static uint32_t init_ddr(void); rev.0.04 */
27/* static uint32_t recovery_from_backup_mode(void); rev.0.04 */
28/* int32_t dram_update_boot_status(uint32_t status); rev.0.04 */
29
30/* rev.0.03 add Comment */
31/*******************************************************************************
32 * register write/read function
33 ******************************************************************************/
34static void WriteReg_32(uint32_t a, uint32_t v)
35{
36 (*(volatile uint32_t*)(uintptr_t)a) = v;
37} /* WriteReg_32 */
38
39static uint32_t ReadReg_32(uint32_t a)
40{
41 uint32_t w = (*(volatile uint32_t*)(uintptr_t)a);
42 return w;
43} /* ReadReg_32 */
44
45/* rev.0.04 add Comment */
46/*******************************************************************************
47 * Initialize ddr
48 ******************************************************************************/
49uint32_t init_ddr(void)
50{
51
52 uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i;
53 uint32_t ddr_md;
54
55/* rev.0.08 */
56 uint32_t RegVal,j;
57 uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
58 uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
59 uint32_t pdqsr_ctl,lcdl_ctl,lcdl_judge1,lcdl_judge2;
60
61/* rev.0.08 */
62 if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
63 pdqsr_ctl = 1;
64 lcdl_ctl = 1;
65 }else {
66 pdqsr_ctl = 0;
67 lcdl_ctl = 0;
68 }
69
70 /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
71 ddr_md = (ReadReg_32(RST_MODEMR)>>19)&BIT0;
72
73 /* 1584Mbps setting */
74 if (ddr_md==0){
75 /* CPG setting ===============================================*/
76 WriteReg_32(CPG_CPGWPR,0x5A5AFFFF);
77 WriteReg_32(CPG_CPGWPCR,0xA5A50000);
78
79 WriteReg_32(CPG_SRCR4,0x20000000);
80
81 WriteReg_32(0xE61500DC,0xe2200000); /* Change to 1584Mbps */
82 while ( (BIT11 & ReadReg_32(CPG_PLLECR)) == 0 );
83
84 WriteReg_32(CPG_SRSTCLR4,0x20000000);
85
86 WriteReg_32(CPG_CPGWPCR,0xA5A50001);
87
88 /* CPG setting ===============================================*/
89 } /* ddr_md */
90
91 WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
92 WriteReg_32(DBSC_E3_DBKIND,0x00000007);
93
94
95#if RCAR_DRAM_DDR3L_MEMCONF == 0
96 WriteReg_32(DBSC_E3_DBMEMCONF00,0x0f030a02); /* 1GB */
97#elif RCAR_DRAM_DDR3L_MEMCONF == 1
98 WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02); /* 2GB(default) */
99#elif RCAR_DRAM_DDR3L_MEMCONF == 2
100 WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030b02); /* 4GB */
101#else
102 WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02); /* 2GB */
103#endif
104
105#if RCAR_DRAM_DDR3L_MEMDUAL == 1
106 RegVal_R2 = (ReadReg_32(0xE6790614));
107 WriteReg_32(0xE6790614,RegVal_R2 | 0x00000003); /* MCS1_N/MODT1 are activated. */
108#endif
109
110
111
112 WriteReg_32(DBSC_E3_DBPHYCONF0,0x00000001);
113
114 /* Select setting value in bps */
115 if (ddr_md==0){ /* 1584Mbps */
116 WriteReg_32(DBSC_E3_DBTR0,0x0000000B);
117 WriteReg_32(DBSC_E3_DBTR1,0x00000008);
118 } else { /* 1856Mbps */
119 WriteReg_32(DBSC_E3_DBTR0,0x0000000D);
120 WriteReg_32(DBSC_E3_DBTR1,0x00000009);
121 } /* ddr_md */
122
123 WriteReg_32(DBSC_E3_DBTR2,0x00000000);
124
125 /* Select setting value in bps */
126 if (ddr_md==0){ /* 1584Mbps */
127 WriteReg_32(DBSC_E3_DBTR3,0x0000000B);
128 WriteReg_32(DBSC_E3_DBTR4,0x000B000B);
129 WriteReg_32(DBSC_E3_DBTR5,0x00000027);
130 WriteReg_32(DBSC_E3_DBTR6,0x0000001C);
131 } else { /* 1856Mbps */
132 WriteReg_32(DBSC_E3_DBTR3,0x0000000D);
133 WriteReg_32(DBSC_E3_DBTR4,0x000D000D);
134 WriteReg_32(DBSC_E3_DBTR5,0x0000002D);
135 WriteReg_32(DBSC_E3_DBTR6,0x00000020);
136 } /* ddr_md */
137
138 WriteReg_32(DBSC_E3_DBTR7,0x00060006);
139
140 /* Select setting value in bps */
141 if (ddr_md==0){ /* 1584Mbps */
142 WriteReg_32(DBSC_E3_DBTR8,0x00000020);
143 WriteReg_32(DBSC_E3_DBTR9,0x00000006);
144 WriteReg_32(DBSC_E3_DBTR10,0x0000000C);
145 WriteReg_32(DBSC_E3_DBTR11,0x0000000A);
146 WriteReg_32(DBSC_E3_DBTR12,0x00120012);
147 WriteReg_32(DBSC_E3_DBTR13,0x000000CE);
148 WriteReg_32(DBSC_E3_DBTR14,0x00140005);
149 WriteReg_32(DBSC_E3_DBTR15,0x00050004);
150 WriteReg_32(DBSC_E3_DBTR16,0x071F0305);
151 WriteReg_32(DBSC_E3_DBTR17,0x040C0000);
152 } else { /* 1856Mbps */
153 WriteReg_32(DBSC_E3_DBTR8,0x00000021);
154 WriteReg_32(DBSC_E3_DBTR9,0x00000007);
155 WriteReg_32(DBSC_E3_DBTR10,0x0000000E);
156 WriteReg_32(DBSC_E3_DBTR11,0x0000000C);
157 WriteReg_32(DBSC_E3_DBTR12,0x00140014);
158 WriteReg_32(DBSC_E3_DBTR13,0x000000F2);
159 WriteReg_32(DBSC_E3_DBTR14,0x00170006);
160 WriteReg_32(DBSC_E3_DBTR15,0x00060005);
161 WriteReg_32(DBSC_E3_DBTR16,0x09210507);
162 WriteReg_32(DBSC_E3_DBTR17,0x040E0000);
163 } /* ddr_md */
164
165 WriteReg_32(DBSC_E3_DBTR18,0x00000200);
166
167 /* Select setting value in bps */
168 if (ddr_md==0){ /* 1584Mbps */
169 WriteReg_32(DBSC_E3_DBTR19,0x01000040);
170 WriteReg_32(DBSC_E3_DBTR20,0x020000D6);
171 } else { /* 1856Mbps */
172 WriteReg_32(DBSC_E3_DBTR19,0x0129004B);
173 WriteReg_32(DBSC_E3_DBTR20,0x020000FB);
174 } /* ddr_md */
175
176 WriteReg_32(DBSC_E3_DBTR21,0x00040004);
177 WriteReg_32(DBSC_E3_DBBL,0x00000000);
178 WriteReg_32(DBSC_E3_DBODT0,0x00000001);
179 WriteReg_32(DBSC_E3_DBADJ0,0x00000001);
180 WriteReg_32(DBSC_E3_DBSYSCONF1,0x00000002);
181 WriteReg_32(DBSC_E3_DBDFICNT0,0x00000010);
182 WriteReg_32(DBSC_E3_DBBCAMDIS,0x00000001);
183 WriteReg_32(DBSC_E3_DBSCHRW1,0x00000046);
184
185 /* Select setting value in bps */
186 if (ddr_md==0){ /* 1584Mbps */
187 WriteReg_32(DBSC_E3_SCFCTST0,0x0D050B03);
188 WriteReg_32(DBSC_E3_SCFCTST1,0x0306030C);
189 } else { /* 1856Mbps */
190 WriteReg_32(DBSC_E3_SCFCTST0,0x0C050B03);
191 WriteReg_32(DBSC_E3_SCFCTST1,0x0305030C);
192 } /* ddr_md */
193
194 /* rev.0.03 add Comment */
195 /****************************************************************************
196 * Initial_Step0( INITBYP )
197 ***************************************************************************/
198 WriteReg_32(DBSC_E3_DBPDLK0,0x0000A55A);
199 WriteReg_32(DBSC_E3_DBCMD,0x01840001);
200 WriteReg_32(DBSC_E3_DBCMD,0x08840000);
201 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
202 WriteReg_32(DBSC_E3_DBPDRGD0,0x80010000);
203 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
204 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
205
206 /* rev.0.03 add Comment */
207 /****************************************************************************
208 * Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training )
209 ***************************************************************************/
210 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000008);
211 WriteReg_32(DBSC_E3_DBPDRGD0,0x000B8000);
212 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
213
214 /* Select setting value in bps */
215 if (ddr_md==0){ /* 1584Mbps */
216 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058904);
217 } else { /* 1856Mbps */
218 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A04);
219 } /* ddr_md */
220
221 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000091);
222 WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
223 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000095);
224 WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BBAD);
225 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000099);
226 WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
227 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
228
229 /* Select setting value in bps */
230 if (ddr_md==0){ /* 1584Mbps */
231 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
232 } else { /* 1856Mbps */
233 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
234 } /* ddr_md */
235
236 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
237 WriteReg_32(DBSC_E3_DBPDRGD0,0x0024641E);
238 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
239 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010073);
240 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
241 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
242
243 /* rev.0.03 add Comment */
244 /****************************************************************************
245 * Initial_Step2( DRAMRST/DRAMINT training )
246 ***************************************************************************/
247 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
248
249 /* Select setting value in bps */
250 if (ddr_md==0){ /* 1584Mbps */
251 WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058900);
252 } else { /* 1856Mbps */
253 WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058A00);
254 } /* ddr_md */
255
256 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
257
258 /* Select setting value in bps */
259 if (ddr_md==0){ /* 1584Mbps */
260 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
261 } else { /* 1856Mbps */
262 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
263 } /* ddr_md */
264
265 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
266 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
267
268 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
269 WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
270 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
271 while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
272
273 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000004);
274
275 /* Select setting value in bps */
276 if (ddr_md==0){ /* 1584Mbps */
277 WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*792/125)-400 + 0x08B00000);
278 } else { /* 1856Mbps */
279 WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*928/125)-400 + 0x0A300000);
280 } /* ddr_md */
281
282 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000022);
283 WriteReg_32(DBSC_E3_DBPDRGD0,0x1000040B);
284 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000023);
285
286 /* Select setting value in bps */
287 if (ddr_md==0){ /* 1584Mbps */
288 WriteReg_32(DBSC_E3_DBPDRGD0,0x2D9C0B66);
289 } else { /* 1856Mbps */
290 WriteReg_32(DBSC_E3_DBPDRGD0,0x35A00D77);
291 } /* ddr_md */
292
293 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000024);
294
295 /* Select setting value in bps */
296 if (ddr_md==0){ /* 1584Mbps */
297 WriteReg_32(DBSC_E3_DBPDRGD0,0x2A88B400);
298 } else { /* 1856Mbps */
299 WriteReg_32(DBSC_E3_DBPDRGD0,0x2A8A2C28);
300 } /* ddr_md */
301
302 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000025);
303
304 /* Select setting value in bps */
305 if (ddr_md==0){ /* 1584Mbps */
306 WriteReg_32(DBSC_E3_DBPDRGD0,0x30005200);
307 } else { /* 1856Mbps */
308 WriteReg_32(DBSC_E3_DBPDRGD0,0x30005E00);
309 } /* ddr_md */
310
311 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000026);
312
313 /* Select setting value in bps */
314 if (ddr_md==0){ /* 1584Mbps */
315 WriteReg_32(DBSC_E3_DBPDRGD0,0x0014A9C9);
316 } else { /* 1856Mbps */
317 WriteReg_32(DBSC_E3_DBPDRGD0,0x0014CB49);
318 } /* ddr_md */
319
320 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000027);
321
322 /* Select setting value in bps */
323 if (ddr_md==0){ /* 1584Mbps */
324 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000D70);
325 } else { /* 1856Mbps */
326 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000F14);
327 } /* ddr_md */
328
329 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000028);
330 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000046);
331 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000029);
332
333 /* Select setting value in bps */
334 if (ddr_md==0){ /* 1584Mbps */
335 if (REFRESH_RATE > 3900) {
336 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000018); /* [7]SRT=0 */
337 } else {
338 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000098); /* [7]SRT=1 */
339 }
340 } else { /* 1856Mbps */
341 if (REFRESH_RATE > 3900) {
342 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000020); /* [7]SRT=0 */
343 } else {
344 WriteReg_32(DBSC_E3_DBPDRGD0,0x000000A0); /* [7]SRT=1 */
345 } /* REFRESH_RATE */
346 } /* ddr_md */
347
348 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
349 WriteReg_32(DBSC_E3_DBPDRGD0,0x81003047);
350 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000020);
351 WriteReg_32(DBSC_E3_DBPDRGD0,0x00181884);
352 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000001A);
353 WriteReg_32(DBSC_E3_DBPDRGD0,0x33C03C10);
354 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
355 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
356
357 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A7);
358 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
359 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A8);
360 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
361 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A9);
362 WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
363 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C7);
364 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
365 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C8);
366 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
367 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C9);
368 WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
369 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E7);
370 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
371 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E8);
372 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
373 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E9);
374 WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
375 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000107);
376 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
377 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000108);
378 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
379 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000109);
380 WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
381
382 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
383 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010181);
384 WriteReg_32(DBSC_E3_DBCMD,0x08840001);
385 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
386 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
387
388 /* rev.0.03 add Comment */
389 /****************************************************************************
390 * Initial_Step3( WL/QSG training )
391 ***************************************************************************/
392 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
393 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010601);
394 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
395 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
396
397 /* rev.0.03 add Comment */
398 /****************************************************************************
399 * Initial_Step4( WLADJ training )
400 ***************************************************************************/
401 for ( i = 0; i<4; i++){
402 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
403 RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8;
404 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
405 RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
406 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
407 RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
408 if ( RegVal_R6 > 0 ){
409 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
410 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
411 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
412 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
413 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
414 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
415 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
416 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R6);
417 } else {
418 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
419 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
420 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
421 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R7);
422 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
423 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
424 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
425 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
426 } /* RegVal_R6 */
427 } /* for i */
428
429 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
430 WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00C0);
431
432 /* rev.0.08 */
433 if (pdqsr_ctl == 1){}else{
434
435 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
436 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
437 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
438 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
439 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
440 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
441 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
442 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
443
444 }
445
446 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
447 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010801);
448 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
449 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
450
451 /* rev.0.03 add Comment */
452 /****************************************************************************
453 * Initial_Step5678( RdWrbitRdWreye )
454 ***************************************************************************/
455 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
456 WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00D8);
457
458 /* rev.0.08 */
459 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
460 WriteReg_32(DBSC_E3_DBPDRGD0,0x00011001);
461 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
462 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
463
464if (pdqsr_ctl == 1){
465 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
466 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
467 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
468 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
469 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
470 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
471 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
472 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
473}
474
475 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
476 WriteReg_32(DBSC_E3_DBPDRGD0,0x00012001);
477 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
478 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
479
480if (pdqsr_ctl == 1){
481 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
482 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
483 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
484 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
485 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
486 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
487 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
488 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
489}
490
491 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
492 WriteReg_32(DBSC_E3_DBPDRGD0,0x00014001);
493 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
494 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
495
496if (pdqsr_ctl == 1){
497 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
498 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
499 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
500 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
501 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
502 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
503 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
504 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
505}
506
507 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
508 WriteReg_32(DBSC_E3_DBPDRGD0,0x00018001);
509 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
510 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
511
512 /* rev.0.03 add Comment */
513 /****************************************************************************
514 * Initial_Step3_2( DQS Gate Training )
515 ***************************************************************************/
516 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
517 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
518 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
519 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
520 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
521 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
522 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
523 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
524 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
525 WriteReg_32(DBSC_E3_DBPDRGD0,0x81003087);
526 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
527 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010401);
528 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
529 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
530
531 /* rev.0.03 add Comment */
532 /****************************************************************************
533 * Initial_Step5-2_7-2( Rd bit Rd eye )
534 ***************************************************************************/
535 for ( i = 0; i < 4; i++){
536 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
537 RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8);
538 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
539 RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
540 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
541 RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
542 RegVal_R12 = (RegVal_R5 >> 0x2);
543 if ( RegVal_R12 < RegVal_R6 ){
544 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
545 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
546 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
547 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
548 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
549 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
550 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
551 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
552 } else {
553 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
554 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
555 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
556 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
557 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
558 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
559 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
560 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
561 } /* RegVal_R12 < RegVal_R6 */
562 } /* for i */
563
564/* rev.0.08 */
565 if (pdqsr_ctl == 1){}else{
566
567 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
568 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
569 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
570 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
571 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
572 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
573 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
574 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
575
576 }
577
578 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
579 WriteReg_32(DBSC_E3_DBPDRGD0,0x00015001);
580 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
581 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
582
583
584/* rev.0.08 */
585 if (lcdl_ctl == 1){
586 for (i=0; i< 4; i++) {
587 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
588 dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
589 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
590 bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8);
591 bdlcount_0c_div2 = (bdlcount_0c >> 1);
592 bdlcount_0c_div4 = (bdlcount_0c >> 2);
593 bdlcount_0c_div8 = (bdlcount_0c >> 3);
594 bdlcount_0c_div16 = (bdlcount_0c >> 4);
595
596 if (ddr_md==0){ /* 1584Mbps */
597 lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8 ;
598 lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16 ;
599 } else { /* 1856Mbps */
600 lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 ;
601 lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 ;
602 } /* ddr_md */
603
604 if (dqsgd_0c > lcdl_judge1) {
605 if (dqsgd_0c <= lcdl_judge2) {
606 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
607 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
608 WriteReg_32(DBSC_E3_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal));
609 } else {
610 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
611 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
612 WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
613 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
614 gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
615 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
616 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
617 WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal|(gatesl_0c + 1)));
618 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
619 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
620 rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
621 rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
622 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
623 WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16)));
624 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
625 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
626 rbd_0c[0] = (RegVal ) & 0x0000001f;
627 rbd_0c[1] = (RegVal >> 8) & 0x0000001f;
628 rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
629 rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
630 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
631 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
632 for (j=0; j< 4; j++) {
633 rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
634 if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
635 RegVal = RegVal | (rbd_0c[j] <<8*j);
636 }
637 WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
638 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
639 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
640 rbd_0c[0] = (RegVal ) & 0x0000001f;
641 rbd_0c[1] = (RegVal >> 8) & 0x0000001f;
642 rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
643 rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
644 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
645 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
646 for (j=0; j< 4; j++) {
647 rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
648 if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
649 RegVal = RegVal | (rbd_0c[j] <<8*j);
650 }
651 WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
652 }
653 }
654 }
655 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000002);
656 WriteReg_32(DBSC_E3_DBPDRGD0,0x07D81E37);
657 }
658
659
660 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
661 WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
662 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
663 while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0 );
664
665 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
666 WriteReg_32(DBSC_E3_DBPDRGD0,0x0024643E);
667
668 WriteReg_32(DBSC_E3_DBBUS0CNF1,0x00000010);
669 WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000/REFRESH_RATE) + 0x01000000);
670 /* Select setting value in bps */
671 if (ddr_md==0){ /* 1584Mbps */
672 WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*99/125) + 0x00080000);
673 } else { /* 1856Mbps */
674 WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*116/125) + 0x00080000);
675 } /* ddr_md */
676
677 WriteReg_32(DBSC_E3_DBRFCNF2,0x00010000);
678 WriteReg_32(DBSC_E3_DBDFICUPDCNF,0x40100001);
679 WriteReg_32(DBSC_E3_DBRFEN,0x00000001);
680 WriteReg_32(DBSC_E3_DBACEN,0x00000001);
681
682/* rev.0.08 */
683 if (pdqsr_ctl == 1){
684 WriteReg_32(0xE67F0018,0x00000001);
685 RegVal = ReadReg_32(0x40000000);
686 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000000);
687 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal);
688 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
689 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
690 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
691 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
692 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
693 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
694 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
695 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
696
697 }
698
699
700 /* rev.0.03 add Comment */
701 /****************************************************************************
702 * Initial_Step9( Initial End )
703 ***************************************************************************/
704 WriteReg_32(DBSC_E3_DBPDLK0,0x00000000);
705 WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
706
707#ifdef ddr_qos_init_setting /* only for non qos_init */
708 WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
709 WriteReg_32(DBSC_E3_DBCAM0CNF1,0x00043218);
710 WriteReg_32(DBSC_E3_DBCAM0CNF2,0x000000F4);
711 WriteReg_32(DBSC_E3_DBSCHCNT0,0x000f0037);
712 WriteReg_32(DBSC_E3_DBSCHSZ0,0x00000001);
713 WriteReg_32(DBSC_E3_DBSCHRW0,0x22421111);
714 WriteReg_32(DBSC_E3_SCFCTST2,0x012F1123);
715 WriteReg_32(DBSC_E3_DBSCHQOS00,0x00000F00);
716 WriteReg_32(DBSC_E3_DBSCHQOS01,0x00000B00);
717 WriteReg_32(DBSC_E3_DBSCHQOS02,0x00000000);
718 WriteReg_32(DBSC_E3_DBSCHQOS03,0x00000000);
719 WriteReg_32(DBSC_E3_DBSCHQOS40,0x00000300);
720 WriteReg_32(DBSC_E3_DBSCHQOS41,0x000002F0);
721 WriteReg_32(DBSC_E3_DBSCHQOS42,0x00000200);
722 WriteReg_32(DBSC_E3_DBSCHQOS43,0x00000100);
723 WriteReg_32(DBSC_E3_DBSCHQOS90,0x00000100);
724 WriteReg_32(DBSC_E3_DBSCHQOS91,0x000000F0);
725 WriteReg_32(DBSC_E3_DBSCHQOS92,0x000000A0);
726 WriteReg_32(DBSC_E3_DBSCHQOS93,0x00000040);
727 WriteReg_32(DBSC_E3_DBSCHQOS130,0x00000100);
728 WriteReg_32(DBSC_E3_DBSCHQOS131,0x000000F0);
729 WriteReg_32(DBSC_E3_DBSCHQOS132,0x000000A0);
730 WriteReg_32(DBSC_E3_DBSCHQOS133,0x00000040);
731 WriteReg_32(DBSC_E3_DBSCHQOS140,0x000000C0);
732 WriteReg_32(DBSC_E3_DBSCHQOS141,0x000000B0);
733 WriteReg_32(DBSC_E3_DBSCHQOS142,0x00000080);
734 WriteReg_32(DBSC_E3_DBSCHQOS143,0x00000040);
735 WriteReg_32(DBSC_E3_DBSCHQOS150,0x00000040);
736 WriteReg_32(DBSC_E3_DBSCHQOS151,0x00000030);
737 WriteReg_32(DBSC_E3_DBSCHQOS152,0x00000020);
738 WriteReg_32(DBSC_E3_DBSCHQOS153,0x00000010);
739
740/* rev.0.08 */
741 if (pdqsr_ctl == 1){}else{
742 WriteReg_32(0xE67F0018,0x00000001);
743 }
744
745 WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
746#endif
747
748 return 1; /* rev.0.04 Restore the return code */
749
750} /* init_ddr */
751
752/* rev.0.04 add function */
753uint32_t recovery_from_backup_mode(void)
754{
755
756 /****************************************************************************
757 * recovery_Step0(DBSC Setting 1) / same "init_ddr"
758 ***************************************************************************/
759 uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i;
760 uint32_t ddr_md;
761 uint32_t err;
762
763
764/* rev.0.08 */
765 uint32_t RegVal,j;
766 uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
767 uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
768 uint32_t pdqsr_ctl,lcdl_ctl,lcdl_judge1,lcdl_judge2;
769
770/* rev.0.08 */
771 if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
772 pdqsr_ctl = 1;
773 lcdl_ctl = 1;
774 }else {
775 pdqsr_ctl = 0;
776 lcdl_ctl = 0;
777 }
778
779
780 /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
781 ddr_md = (ReadReg_32(RST_MODEMR)>>19)&BIT0;
782
783 /* 1584Mbps setting */
784 if (ddr_md==0){
785 /* CPG setting ===============================================*/
786 WriteReg_32(CPG_CPGWPR,0x5A5AFFFF);
787 WriteReg_32(CPG_CPGWPCR,0xA5A50000);
788
789 WriteReg_32(CPG_SRCR4,0x20000000);
790
791 WriteReg_32(0xE61500DC,0xe2200000); /* Change to 1584Mbps */
792 while ( (BIT11 & ReadReg_32(CPG_PLLECR)) == 0 );
793
794 WriteReg_32(CPG_SRSTCLR4,0x20000000);
795
796 WriteReg_32(CPG_CPGWPCR,0xA5A50001);
797
798 /* CPG setting ===============================================*/
799 } /* ddr_md */
800
801 WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
802 WriteReg_32(DBSC_E3_DBKIND,0x00000007);
803
804#if RCAR_DRAM_DDR3L_MEMCONF == 0
805 WriteReg_32(DBSC_E3_DBMEMCONF00,0x0f030a02);
806#elif RCAR_DRAM_DDR3L_MEMCONF == 1
807 WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02);
808#elif RCAR_DRAM_DDR3L_MEMCONF == 2
809 WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030b02);
810#else
811 WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02);
812#endif
813
814/* rev.0.08 */
815#if RCAR_DRAM_DDR3L_MEMDUAL == 1
816 RegVal_R2 = (ReadReg_32(0xE6790614));
817 WriteReg_32(0xE6790614,RegVal_R2 | 0x00000003); /* MCS1_N/MODT1 are activated. */
818#endif
819
820 WriteReg_32(DBSC_E3_DBPHYCONF0,0x00000001);
821
822 /* Select setting value in bps */
823 if (ddr_md==0){ /* 1584Mbps */
824 WriteReg_32(DBSC_E3_DBTR0,0x0000000B);
825 WriteReg_32(DBSC_E3_DBTR1,0x00000008);
826 } else { /* 1856Mbps */
827 WriteReg_32(DBSC_E3_DBTR0,0x0000000D);
828 WriteReg_32(DBSC_E3_DBTR1,0x00000009);
829 } /* ddr_md */
830
831 WriteReg_32(DBSC_E3_DBTR2,0x00000000);
832
833 /* Select setting value in bps */
834 if (ddr_md==0){ /* 1584Mbps */
835 WriteReg_32(DBSC_E3_DBTR3,0x0000000B);
836 WriteReg_32(DBSC_E3_DBTR4,0x000B000B);
837 WriteReg_32(DBSC_E3_DBTR5,0x00000027);
838 WriteReg_32(DBSC_E3_DBTR6,0x0000001C);
839 } else { /* 1856Mbps */
840 WriteReg_32(DBSC_E3_DBTR3,0x0000000D);
841 WriteReg_32(DBSC_E3_DBTR4,0x000D000D);
842 WriteReg_32(DBSC_E3_DBTR5,0x0000002D);
843 WriteReg_32(DBSC_E3_DBTR6,0x00000020);
844 } /* ddr_md */
845
846 WriteReg_32(DBSC_E3_DBTR7,0x00060006);
847
848 /* Select setting value in bps */
849 if (ddr_md==0){ /* 1584Mbps */
850 WriteReg_32(DBSC_E3_DBTR8,0x00000020);
851 WriteReg_32(DBSC_E3_DBTR9,0x00000006);
852 WriteReg_32(DBSC_E3_DBTR10,0x0000000C);
853 WriteReg_32(DBSC_E3_DBTR11,0x0000000A);
854 WriteReg_32(DBSC_E3_DBTR12,0x00120012);
855 WriteReg_32(DBSC_E3_DBTR13,0x000000CE);
856 WriteReg_32(DBSC_E3_DBTR14,0x00140005);
857 WriteReg_32(DBSC_E3_DBTR15,0x00050004);
858 WriteReg_32(DBSC_E3_DBTR16,0x071F0305);
859 WriteReg_32(DBSC_E3_DBTR17,0x040C0000);
860 } else { /* 1856Mbps */
861 WriteReg_32(DBSC_E3_DBTR8,0x00000021);
862 WriteReg_32(DBSC_E3_DBTR9,0x00000007);
863 WriteReg_32(DBSC_E3_DBTR10,0x0000000E);
864 WriteReg_32(DBSC_E3_DBTR11,0x0000000C);
865 WriteReg_32(DBSC_E3_DBTR12,0x00140014);
866 WriteReg_32(DBSC_E3_DBTR13,0x000000F2);
867 WriteReg_32(DBSC_E3_DBTR14,0x00170006);
868 WriteReg_32(DBSC_E3_DBTR15,0x00060005);
869 WriteReg_32(DBSC_E3_DBTR16,0x09210507);
870 WriteReg_32(DBSC_E3_DBTR17,0x040E0000);
871 } /* ddr_md */
872
873 WriteReg_32(DBSC_E3_DBTR18,0x00000200);
874
875 /* Select setting value in bps */
876 if (ddr_md==0){ /* 1584Mbps */
877 WriteReg_32(DBSC_E3_DBTR19,0x01000040);
878 WriteReg_32(DBSC_E3_DBTR20,0x020000D6);
879 } else { /* 1856Mbps */
880 WriteReg_32(DBSC_E3_DBTR19,0x0129004B);
881 WriteReg_32(DBSC_E3_DBTR20,0x020000FB);
882 } /* ddr_md */
883
884 WriteReg_32(DBSC_E3_DBTR21,0x00040004);
885 WriteReg_32(DBSC_E3_DBBL,0x00000000);
886 WriteReg_32(DBSC_E3_DBODT0,0x00000001);
887 WriteReg_32(DBSC_E3_DBADJ0,0x00000001);
888 WriteReg_32(DBSC_E3_DBSYSCONF1,0x00000002);
889 WriteReg_32(DBSC_E3_DBDFICNT0,0x00000010);
890 WriteReg_32(DBSC_E3_DBBCAMDIS,0x00000001);
891 WriteReg_32(DBSC_E3_DBSCHRW1,0x00000046);
892
893 /* Select setting value in bps */
894 if (ddr_md==0){ /* 1584Mbps */
895 WriteReg_32(DBSC_E3_SCFCTST0,0x0D050B03);
896 WriteReg_32(DBSC_E3_SCFCTST1,0x0306030C);
897 } else { /* 1856Mbps */
898 WriteReg_32(DBSC_E3_SCFCTST0,0x0C050B03);
899 WriteReg_32(DBSC_E3_SCFCTST1,0x0305030C);
900 } /* ddr_md */
901
902 /****************************************************************************
903 * recovery_Step1(PHY setting 1)
904 ***************************************************************************/
905 WriteReg_32(DBSC_E3_DBPDLK0,0x0000A55A);
906 WriteReg_32(DBSC_E3_DBCMD,0x01840001);
907 WriteReg_32(DBSC_E3_DBCMD,0x0A840000);
908 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000008); /* DDR_PLLCR */
909 WriteReg_32(DBSC_E3_DBPDRGD0,0x000B8000);
910 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003); /* DDR_PGCR1 */
911 WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
912 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000020); /* DDR_DXCCR */
913 WriteReg_32(DBSC_E3_DBPDRGD0,0x00181884);
914 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000001A); /* DDR_ACIOCR0 */
915 WriteReg_32(DBSC_E3_DBPDRGD0,0x33C03C10);
916 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
917 while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
918
919 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000004);
920
921 /* Select setting value in bps */
922 if (ddr_md==0){ /* 1584Mbps */
923 WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*792/125)-400 + 0x08B00000);
924 } else { /* 1856Mbps */
925 WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*928/125)-400 + 0x0A300000);
926 } /* ddr_md */
927
928 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000022);
929 WriteReg_32(DBSC_E3_DBPDRGD0,0x1000040B);
930 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000023);
931
932 /* Select setting value in bps */
933 if (ddr_md==0){ /* 1584Mbps */
934 WriteReg_32(DBSC_E3_DBPDRGD0,0x2D9C0B66);
935 } else { /* 1856Mbps */
936 WriteReg_32(DBSC_E3_DBPDRGD0,0x35A00D77);
937 } /* ddr_md */
938
939 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000024);
940
941 /* Select setting value in bps */
942 if (ddr_md==0){ /* 1584Mbps */
943 WriteReg_32(DBSC_E3_DBPDRGD0,0x2A88B400);
944 } else { /* 1856Mbps */
945 WriteReg_32(DBSC_E3_DBPDRGD0,0x2A8A2C28);
946 } /* ddr_md */
947
948 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000025);
949
950 /* Select setting value in bps */
951 if (ddr_md==0){ /* 1584Mbps */
952 WriteReg_32(DBSC_E3_DBPDRGD0,0x30005200);
953 } else { /* 1856Mbps */
954 WriteReg_32(DBSC_E3_DBPDRGD0,0x30005E00);
955 } /* ddr_md */
956
957 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000026);
958
959 /* Select setting value in bps */
960 if (ddr_md==0){ /* 1584Mbps */
961 WriteReg_32(DBSC_E3_DBPDRGD0,0x0014A9C9);
962 } else { /* 1856Mbps */
963 WriteReg_32(DBSC_E3_DBPDRGD0,0x0014CB49);
964 } /* ddr_md */
965
966 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000027);
967
968 /* Select setting value in bps */
969 if (ddr_md==0){ /* 1584Mbps */
970 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000D70);
971 } else { /* 1856Mbps */
972 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000F14);
973 } /* ddr_md */
974
975 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000028);
976 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000046);
977 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000029);
978
979 /* Select setting value in bps */
980 if (ddr_md==0){ /* 1584Mbps */
981 if (REFRESH_RATE > 3900) {
982 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000018); /* [7]SRT=0 */
983 } else {
984 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000098); /* [7]SRT=1 */
985 }
986 } else { /* 1856Mbps */
987 if (REFRESH_RATE > 3900) {
988 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000020); /* [7]SRT=0 */
989 } else {
990 WriteReg_32(DBSC_E3_DBPDRGD0,0x000000A0); /* [7]SRT=1 */
991 } /* REFRESH_RATE */
992 } /* ddr_md */
993
994 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
995 WriteReg_32(DBSC_E3_DBPDRGD0,0x81003047);
996 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000091);
997 WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
998 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000095);
999 WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BBAD);
1000 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000099);
1001 WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
1002 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021); /* DDR_DSGCR */
1003 WriteReg_32(DBSC_E3_DBPDRGD0,0x0024641E);
1004 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
1005 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1006
1007 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
1008 WriteReg_32(DBSC_E3_DBPDRGD0,0x40010000);
1009
1010 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
1011 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1012
1013 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000092); /* DDR_ZQ0DR */
1014 WriteReg_32(DBSC_E3_DBPDRGD0,0xC2C59AB5);
1015 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000096); /* DDR_ZQ1DR */
1016 WriteReg_32(DBSC_E3_DBPDRGD0,0xC4285FBF);
1017 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000009A); /* DDR_ZQ2DR */
1018 WriteReg_32(DBSC_E3_DBPDRGD0,0xC2C59AB5);
1019 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /* DDR_ZQCR */
1020
1021 /* Select setting value in bps */
1022 if (ddr_md==0){ /* 1584Mbps */
1023 WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058900);
1024 } else { /* 1856Mbps */
1025 WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058A00);
1026 } /* ddr_md */
1027
1028 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /* DDR_ZQCR */
1029
1030 /* Select setting value in bps */
1031 if (ddr_md==0){ /* 1584Mbps */
1032 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
1033 } else { /* 1856Mbps */
1034 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
1035 } /* ddr_md */
1036
1037 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
1038 WriteReg_32(DBSC_E3_DBPDRGD0,0x00050001);
1039
1040 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
1041 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1042
1043 /* ddr backupmode end */
1044 if(ddrBackup) {
1045 NOTICE("[WARM_BOOT]");
1046 } else {
1047 NOTICE("[COLD_BOOT]");
1048 } /* ddrBackup */
ldts0a596b42018-11-06 10:17:12 +0100[diff] [blame]1049 err=rcar_dram_update_boot_status(ddrBackup);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1050 if(err){
1051 NOTICE("[BOOT_STATUS_UPDATE_ERROR]");
1052 return INITDRAM_ERR_I;
1053 } /* err */
1054
1055 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000092); /* DDR_ZQ0DR */
1056 WriteReg_32(DBSC_E3_DBPDRGD0,0x02C59AB5);
1057 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000096); /* DDR_ZQ1DR */
1058 WriteReg_32(DBSC_E3_DBPDRGD0,0x04285FBF);
1059 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000009A); /* DDR_ZQ2DR */
1060 WriteReg_32(DBSC_E3_DBPDRGD0,0x02C59AB5);
1061
1062 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
1063 WriteReg_32(DBSC_E3_DBPDRGD0,0x08000000);
1064
1065 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
1066 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000003);
1067
1068 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
1069 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1070
1071 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
1072 WriteReg_32(DBSC_E3_DBPDRGD0,0x80010000);
1073
1074 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
1075 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1076
1077 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
1078 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010073);
1079
1080 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
1081 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1082
1083 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /* DDR_ZQCR */
1084
1085 /* Select setting value in bps */
1086 if (ddr_md==0){ /* 1584Mbps */
1087 WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058900);
1088 } else { /* 1856Mbps */
1089 WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058A00);
1090 } /* ddr_md */
1091
1092 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /* DDR_ZQCR */
1093
1094 /* Select setting value in bps */
1095 if (ddr_md==0){ /* 1584Mbps */
1096 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
1097 } else { /* 1856Mbps */
1098 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
1099 } /* ddr_md */
1100
1101/* rev0.08 */
1102 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000000C);
1103 WriteReg_32(DBSC_E3_DBPDRGD0,0x18000040);
1104
1105 /****************************************************************************
1106 * recovery_Step2(PHY setting 2)
1107 ***************************************************************************/
1108 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
1109 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1110
1111 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A7);
1112 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
1113 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A8);
1114 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
1115 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A9);
1116 WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
1117 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C7);
1118 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
1119 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C8);
1120 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
1121 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C9);
1122 WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
1123 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E7);
1124 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
1125 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E8);
1126 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
1127 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E9);
1128 WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
1129 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000107);
1130 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
1131 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000108);
1132 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
1133 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000109);
1134 WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
1135
1136 WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000/REFRESH_RATE) + 0x01000000);
1137 WriteReg_32(DBSC_E3_DBBUS0CNF1,0x00000010);
1138
1139 /* Select setting value in bps */
1140 if (ddr_md==0){ /* 1584Mbps */
1141 WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*99/125) + 0x00080000);
1142 } else { /* 1856Mbps */
1143 WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*116/125) + 0x00080000);
1144 } /* ddr_md */
1145
1146 WriteReg_32(DBSC_E3_DBRFCNF2,0x00010000);
1147 WriteReg_32(DBSC_E3_DBRFEN,0x00000001);
1148 WriteReg_32(DBSC_E3_DBCMD,0x0A840001);
1149 while ( (BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0 );
1150
1151 WriteReg_32(DBSC_E3_DBCMD,0x00000000);
1152
1153 WriteReg_32(DBSC_E3_DBCMD,0x04840010);
1154 while ( (BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0 );
1155
1156 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
1157 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1158
1159 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
1160 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010701);
1161
1162 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
1163 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1164
1165 for ( i = 0; i<4; i++)
1166 {
1167 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
1168 RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8;
1169 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
1170 RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
1171 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
1172 RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
1173
1174 if ( RegVal_R6 > 0 ){
1175 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
1176 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
1177 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
1178 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
1179 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1180 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
1181 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1182 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R6);
1183 } else {
1184 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
1185 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
1186 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
1187 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R7);
1188 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1189 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
1190 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1191 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
1192 } /* RegVal_R6 */
1193 } /* for i */
1194
1195 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
1196 WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00C0);
1197
1198 /* rev.0.08 */
1199 if (pdqsr_ctl == 1){}else{
1200
1201 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
1202 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1203 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
1204 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1205 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
1206 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1207 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
1208 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1209
1210 }
1211
1212 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
1213 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010801);
1214 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
1215 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1216
1217 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
1218 WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00D8);
1219
1220
1221 /* rev.0.08 */
1222 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
1223 WriteReg_32(DBSC_E3_DBPDRGD0,0x00011001);
1224 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
1225 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1226
1227if (pdqsr_ctl == 1){
1228 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
1229 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1230 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
1231 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1232 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
1233 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1234 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
1235 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1236}
1237
1238 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
1239 WriteReg_32(DBSC_E3_DBPDRGD0,0x00012001);
1240 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
1241 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1242
1243if (pdqsr_ctl == 1){
1244 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
1245 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
1246 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
1247 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
1248 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
1249 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
1250 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
1251 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
1252}
1253
1254 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
1255 WriteReg_32(DBSC_E3_DBPDRGD0,0x00014001);
1256 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
1257 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1258
1259if (pdqsr_ctl == 1){
1260 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
1261 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1262 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
1263 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1264 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
1265 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1266 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
1267 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1268}
1269
1270 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
1271 WriteReg_32(DBSC_E3_DBPDRGD0,0x00018001);
1272 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
1273 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1274
1275 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
1276 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
1277 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
1278 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
1279 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
1280 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
1281 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
1282 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
1283 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
1284 WriteReg_32(DBSC_E3_DBPDRGD0,0x81003087);
1285 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
1286 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010401);
1287 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
1288 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1289
1290 for ( i = 0; i < 4; i++){
1291 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
1292 RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8);
1293 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
1294 RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
1295 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
1296 RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
1297 RegVal_R12 = (RegVal_R5 >> 0x2);
1298
1299 if ( RegVal_R12 < RegVal_R6 ){
1300 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
1301 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
1302 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
1303 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
1304 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1305 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
1306 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1307 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
1308 } else {
1309 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
1310 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
1311 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
1312 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
1313 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1314 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
1315 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1316 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
1317 } /* RegVal_R12 < RegVal_R6 */
1318 } /* for i */
1319
1320/* rev.0.08 */
1321 if (pdqsr_ctl == 1){}else{
1322
1323 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
1324 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1325 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
1326 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1327 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
1328 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1329 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
1330 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1331
1332 }
1333
1334 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
1335 WriteReg_32(DBSC_E3_DBPDRGD0,0x00015001);
1336 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
1337 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1338
1339
1340/* rev.0.08 */
1341 if (lcdl_ctl == 1){
1342 for (i=0; i< 4; i++) {
1343 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1344 dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
1345 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
1346 bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8);
1347 bdlcount_0c_div2 = (bdlcount_0c >> 1);
1348 bdlcount_0c_div4 = (bdlcount_0c >> 2);
1349 bdlcount_0c_div8 = (bdlcount_0c >> 3);
1350 bdlcount_0c_div16 = (bdlcount_0c >> 4);
1351
1352 if (ddr_md==0){ /* 1584Mbps */
1353 lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8 ;
1354 lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16 ;
1355 } else { /* 1856Mbps */
1356 lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 ;
1357 lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 ;
1358 } /* ddr_md */
1359
1360 if (dqsgd_0c > lcdl_judge1) {
1361 if (dqsgd_0c <= lcdl_judge2) {
1362 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
1363 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
1364 WriteReg_32(DBSC_E3_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal));
1365 } else {
1366 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
1367 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
1368 WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
1369 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
1370 gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
1371 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
1372 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
1373 WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal|(gatesl_0c + 1)));
1374 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
1375 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
1376 rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
1377 rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
1378 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
1379 WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16)));
1380 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
1381 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
1382 rbd_0c[0] = (RegVal ) & 0x0000001f;
1383 rbd_0c[1] = (RegVal >> 8) & 0x0000001f;
1384 rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
1385 rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
1386 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
1387 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
1388 for (j=0; j< 4; j++) {
1389 rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
1390 if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
1391 RegVal = RegVal | (rbd_0c[j] <<8*j);
1392 }
1393 WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
1394 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
1395 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
1396 rbd_0c[0] = (RegVal ) & 0x0000001f;
1397 rbd_0c[1] = (RegVal >> 8) & 0x0000001f;
1398 rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
1399 rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
1400 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
1401 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
1402 for (j=0; j< 4; j++) {
1403 rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
1404 if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
1405 RegVal = RegVal | (rbd_0c[j] <<8*j);
1406 }
1407 WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
1408 }
1409 }
1410 }
1411 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000002);
1412 WriteReg_32(DBSC_E3_DBPDRGD0,0x07D81E37);
1413 }
1414
1415
1416
1417 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
1418 WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
1419 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
1420 while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0 );
1421 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
1422 WriteReg_32(DBSC_E3_DBPDRGD0,0x0024643E);
1423
1424 /****************************************************************************
1425 * recovery_Step3(DBSC Setting 2)
1426 ***************************************************************************/
1427 WriteReg_32(DBSC_E3_DBDFICUPDCNF,0x40100001);
1428 WriteReg_32(DBSC_E3_DBACEN,0x00000001);
1429
1430/* rev.0.08 */
1431 if (pdqsr_ctl == 1){
1432 WriteReg_32(0xE67F0018,0x00000001);
1433 RegVal = ReadReg_32(0x40000000);
1434 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000000);
1435 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal);
1436 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
1437 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1438 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
1439 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1440 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
1441 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1442 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
1443 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1444
1445 }
1446
1447
1448 WriteReg_32(DBSC_E3_DBPDLK0,0x00000000);
1449 WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
1450
1451#ifdef ddr_qos_init_setting /* only for non qos_init */
1452 WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
1453 WriteReg_32(DBSC_E3_DBCAM0CNF1,0x00043218);
1454 WriteReg_32(DBSC_E3_DBCAM0CNF2,0x000000F4);
1455 WriteReg_32(DBSC_E3_DBSCHCNT0,0x000f0037);
1456 WriteReg_32(DBSC_E3_DBSCHSZ0,0x00000001);
1457 WriteReg_32(DBSC_E3_DBSCHRW0,0x22421111);
1458 WriteReg_32(DBSC_E3_SCFCTST2,0x012F1123);
1459 WriteReg_32(DBSC_E3_DBSCHQOS00,0x00000F00);
1460 WriteReg_32(DBSC_E3_DBSCHQOS01,0x00000B00);
1461 WriteReg_32(DBSC_E3_DBSCHQOS02,0x00000000);
1462 WriteReg_32(DBSC_E3_DBSCHQOS03,0x00000000);
1463 WriteReg_32(DBSC_E3_DBSCHQOS40,0x00000300);
1464 WriteReg_32(DBSC_E3_DBSCHQOS41,0x000002F0);
1465 WriteReg_32(DBSC_E3_DBSCHQOS42,0x00000200);
1466 WriteReg_32(DBSC_E3_DBSCHQOS43,0x00000100);
1467 WriteReg_32(DBSC_E3_DBSCHQOS90,0x00000100);
1468 WriteReg_32(DBSC_E3_DBSCHQOS91,0x000000F0);
1469 WriteReg_32(DBSC_E3_DBSCHQOS92,0x000000A0);
1470 WriteReg_32(DBSC_E3_DBSCHQOS93,0x00000040);
1471 WriteReg_32(DBSC_E3_DBSCHQOS130,0x00000100);
1472 WriteReg_32(DBSC_E3_DBSCHQOS131,0x000000F0);
1473 WriteReg_32(DBSC_E3_DBSCHQOS132,0x000000A0);
1474 WriteReg_32(DBSC_E3_DBSCHQOS133,0x00000040);
1475 WriteReg_32(DBSC_E3_DBSCHQOS140,0x000000C0);
1476 WriteReg_32(DBSC_E3_DBSCHQOS141,0x000000B0);
1477 WriteReg_32(DBSC_E3_DBSCHQOS142,0x00000080);
1478 WriteReg_32(DBSC_E3_DBSCHQOS143,0x00000040);
1479 WriteReg_32(DBSC_E3_DBSCHQOS150,0x00000040);
1480 WriteReg_32(DBSC_E3_DBSCHQOS151,0x00000030);
1481 WriteReg_32(DBSC_E3_DBSCHQOS152,0x00000020);
1482 WriteReg_32(DBSC_E3_DBSCHQOS153,0x00000010);
1483
1484/* rev.0.08 */
1485 if (pdqsr_ctl == 1){}else{
1486 WriteReg_32(0xE67F0018,0x00000001);
1487 }
1488
1489 WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
1490#endif
1491
1492 return 1;
1493
1494} /* recovery_from_backup_mode */
1495
1496/*******************************************************************************
1497 * init_ddr : MD19=0,DDR3L,1584Mbps / MD19=1,DDR3L,1856Mbps
1498 ******************************************************************************/
1499
1500/*******************************************************************************
1501 * DDR Initialize entry for IPL
1502 ******************************************************************************/
ldts0a596b42018-11-06 10:17:12 +0100[diff] [blame]1503int32_t rcar_dram_init(void)
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1504{
1505 uint32_t dataL;
1506 uint32_t failcount;
1507 uint32_t md=0;
1508 uint32_t ddr=0;
1509
1510 md = *((volatile uint32_t*)RST_MODEMR);
1511 ddr = (md & 0x00080000) >> 19;
1512 if(ddr == 0x0){
1513 NOTICE("BL2: DDR1584(%s)", RCAR_E3_DDR_VERSION);
1514 }
1515 else if(ddr == 0x1){
1516 NOTICE("BL2: DDR1856(%s)", RCAR_E3_DDR_VERSION);
1517 } /* ddr */
1518
ldts0a596b42018-11-06 10:17:12 +0100[diff] [blame]1519 rcar_dram_get_boot_status(&ddrBackup);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1520
1521 if(ddrBackup==DRAM_BOOT_STATUS_WARM){
1522 dataL=recovery_from_backup_mode(); /* WARM boot */
1523 } else {
1524 dataL=init_ddr(); /* COLD boot */
1525 } /* ddrBackup */
1526
1527 if(dataL==1){
1528 failcount =0;
1529 } else {
1530 failcount =1;
1531 } /* dataL */
1532
1533 NOTICE("..%d\n",failcount); /* rev.0.05 */
1534
1535 if(failcount==0){
1536 return INITDRAM_OK;
1537 } else {
1538 return INITDRAM_NG;
1539 } /* failcount */
1540} /* InitDram */
1541
1542/*******************************************************************************
1543 * END
1544 ******************************************************************************/