Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __XLAT_TABLES_ARCH_H__ |
| 8 | #define __XLAT_TABLES_ARCH_H__ |
| 9 | |
| 10 | #include <arch.h> |
| 11 | #include <platform_def.h> |
| 12 | #include <xlat_tables_defs.h> |
Antonio Nino Diaz | c013252 | 2017-05-17 16:25:40 +0100 | [diff] [blame^] | 13 | #include "../xlat_tables_private.h" |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 14 | |
| 15 | /* |
| 16 | * In AArch64 state, the MMU may support 4 KB, 16 KB and 64 KB page |
| 17 | * granularity. For 4KB granularity, a level 0 table descriptor doesn't support |
| 18 | * block translation. For 16KB, the same thing happens to levels 0 and 1. For |
| 19 | * 64KB, same for level 1. See section D4.3.1 of the ARMv8-A Architecture |
| 20 | * Reference Manual (DDI 0487A.k) for more information. |
| 21 | * |
| 22 | * The define below specifies the first table level that allows block |
| 23 | * descriptors. |
| 24 | */ |
| 25 | |
| 26 | #if PAGE_SIZE == (4*1024) /* 4KB */ |
| 27 | # define MIN_LVL_BLOCK_DESC 1 |
| 28 | #else /* 16KB or 64KB */ |
| 29 | # define MIN_LVL_BLOCK_DESC 2 |
| 30 | #endif |
| 31 | |
| 32 | /* |
| 33 | * Each platform can define the size of the virtual address space, which is |
| 34 | * defined in PLAT_VIRT_ADDR_SPACE_SIZE. TCR.TxSZ is calculated as 64 minus the |
| 35 | * width of said address space. The value of TCR.TxSZ must be in the range 16 |
| 36 | * to 39 [1], which means that the virtual address space width must be in the |
| 37 | * range 48 to 25 bits. |
| 38 | * |
| 39 | * Here we calculate the initial lookup level from the value of |
| 40 | * PLAT_VIRT_ADDR_SPACE_SIZE. For a 4 KB page size, level 0 supports virtual |
| 41 | * address spaces of widths 48 to 40 bits, level 1 from 39 to 31, and level 2 |
| 42 | * from 30 to 25. Wider or narrower address spaces are not supported. As a |
| 43 | * result, level 3 cannot be used as initial lookup level with 4 KB |
| 44 | * granularity. [2] |
| 45 | * |
| 46 | * For example, for a 35-bit address space (i.e. PLAT_VIRT_ADDR_SPACE_SIZE == |
| 47 | * 1 << 35), TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table |
| 48 | * D4-11 in the ARM ARM, the initial lookup level for an address space like |
| 49 | * that is 1. |
| 50 | * |
| 51 | * See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more |
| 52 | * information: |
| 53 | * [1] Page 1730: 'Input address size', 'For all translation stages'. |
| 54 | * [2] Section D4.2.5 |
| 55 | */ |
| 56 | |
| 57 | #if PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << (64 - TCR_TxSZ_MIN)) |
| 58 | |
| 59 | # error "PLAT_VIRT_ADDR_SPACE_SIZE is too big." |
| 60 | |
| 61 | #elif PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << L0_XLAT_ADDRESS_SHIFT) |
| 62 | |
| 63 | # define XLAT_TABLE_LEVEL_BASE 0 |
| 64 | # define NUM_BASE_LEVEL_ENTRIES \ |
| 65 | (PLAT_VIRT_ADDR_SPACE_SIZE >> L0_XLAT_ADDRESS_SHIFT) |
| 66 | |
| 67 | #elif PLAT_VIRT_ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT) |
| 68 | |
| 69 | # define XLAT_TABLE_LEVEL_BASE 1 |
| 70 | # define NUM_BASE_LEVEL_ENTRIES \ |
| 71 | (PLAT_VIRT_ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) |
| 72 | |
| 73 | #elif PLAT_VIRT_ADDR_SPACE_SIZE >= (1 << (64 - TCR_TxSZ_MAX)) |
| 74 | |
| 75 | # define XLAT_TABLE_LEVEL_BASE 2 |
| 76 | # define NUM_BASE_LEVEL_ENTRIES \ |
| 77 | (PLAT_VIRT_ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT) |
| 78 | |
| 79 | #else |
| 80 | |
| 81 | # error "PLAT_VIRT_ADDR_SPACE_SIZE is too small." |
| 82 | |
| 83 | #endif |
| 84 | |
| 85 | #endif /* __XLAT_TABLES_ARCH_H__ */ |