| Gabriel Fernandez | 1308d75 | 2020-03-11 11:30:34 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef STM32MP1_RCC_H |
| 8 | #define STM32MP1_RCC_H |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | #define RCC_TZCR U(0x00) |
| 13 | #define RCC_OCENSETR U(0x0C) |
| 14 | #define RCC_OCENCLRR U(0x10) |
| 15 | #define RCC_HSICFGR U(0x18) |
| 16 | #define RCC_CSICFGR U(0x1C) |
| 17 | #define RCC_MPCKSELR U(0x20) |
| 18 | #define RCC_ASSCKSELR U(0x24) |
| 19 | #define RCC_RCK12SELR U(0x28) |
| 20 | #define RCC_MPCKDIVR U(0x2C) |
| 21 | #define RCC_AXIDIVR U(0x30) |
| 22 | #define RCC_APB4DIVR U(0x3C) |
| 23 | #define RCC_APB5DIVR U(0x40) |
| 24 | #define RCC_RTCDIVR U(0x44) |
| 25 | #define RCC_MSSCKSELR U(0x48) |
| 26 | #define RCC_PLL1CR U(0x80) |
| 27 | #define RCC_PLL1CFGR1 U(0x84) |
| 28 | #define RCC_PLL1CFGR2 U(0x88) |
| 29 | #define RCC_PLL1FRACR U(0x8C) |
| 30 | #define RCC_PLL1CSGR U(0x90) |
| 31 | #define RCC_PLL2CR U(0x94) |
| 32 | #define RCC_PLL2CFGR1 U(0x98) |
| 33 | #define RCC_PLL2CFGR2 U(0x9C) |
| 34 | #define RCC_PLL2FRACR U(0xA0) |
| 35 | #define RCC_PLL2CSGR U(0xA4) |
| 36 | #define RCC_I2C46CKSELR U(0xC0) |
| 37 | #define RCC_SPI6CKSELR U(0xC4) |
| 38 | #define RCC_UART1CKSELR U(0xC8) |
| 39 | #define RCC_RNG1CKSELR U(0xCC) |
| 40 | #define RCC_CPERCKSELR U(0xD0) |
| 41 | #define RCC_STGENCKSELR U(0xD4) |
| 42 | #define RCC_DDRITFCR U(0xD8) |
| 43 | #define RCC_MP_BOOTCR U(0x100) |
| 44 | #define RCC_MP_SREQSETR U(0x104) |
| 45 | #define RCC_MP_SREQCLRR U(0x108) |
| 46 | #define RCC_MP_GCR U(0x10C) |
| 47 | #define RCC_MP_APRSTCR U(0x110) |
| 48 | #define RCC_MP_APRSTSR U(0x114) |
| 49 | #define RCC_BDCR U(0x140) |
| 50 | #define RCC_RDLSICR U(0x144) |
| 51 | #define RCC_APB4RSTSETR U(0x180) |
| 52 | #define RCC_APB4RSTCLRR U(0x184) |
| 53 | #define RCC_APB5RSTSETR U(0x188) |
| 54 | #define RCC_APB5RSTCLRR U(0x18C) |
| 55 | #define RCC_AHB5RSTSETR U(0x190) |
| 56 | #define RCC_AHB5RSTCLRR U(0x194) |
| 57 | #define RCC_AHB6RSTSETR U(0x198) |
| 58 | #define RCC_AHB6RSTCLRR U(0x19C) |
| 59 | #define RCC_TZAHB6RSTSETR U(0x1A0) |
| 60 | #define RCC_TZAHB6RSTCLRR U(0x1A4) |
| 61 | #define RCC_MP_APB4ENSETR U(0x200) |
| 62 | #define RCC_MP_APB4ENCLRR U(0x204) |
| 63 | #define RCC_MP_APB5ENSETR U(0x208) |
| 64 | #define RCC_MP_APB5ENCLRR U(0x20C) |
| 65 | #define RCC_MP_AHB5ENSETR U(0x210) |
| 66 | #define RCC_MP_AHB5ENCLRR U(0x214) |
| 67 | #define RCC_MP_AHB6ENSETR U(0x218) |
| 68 | #define RCC_MP_AHB6ENCLRR U(0x21C) |
| 69 | #define RCC_MP_TZAHB6ENSETR U(0x220) |
| 70 | #define RCC_MP_TZAHB6ENCLRR U(0x224) |
| 71 | #define RCC_MC_APB4ENSETR U(0x280) |
| 72 | #define RCC_MC_APB4ENCLRR U(0x284) |
| 73 | #define RCC_MC_APB5ENSETR U(0x288) |
| 74 | #define RCC_MC_APB5ENCLRR U(0x28C) |
| 75 | #define RCC_MC_AHB5ENSETR U(0x290) |
| 76 | #define RCC_MC_AHB5ENCLRR U(0x294) |
| 77 | #define RCC_MC_AHB6ENSETR U(0x298) |
| 78 | #define RCC_MC_AHB6ENCLRR U(0x29C) |
| 79 | #define RCC_MP_APB4LPENSETR U(0x300) |
| 80 | #define RCC_MP_APB4LPENCLRR U(0x304) |
| 81 | #define RCC_MP_APB5LPENSETR U(0x308) |
| 82 | #define RCC_MP_APB5LPENCLRR U(0x30C) |
| 83 | #define RCC_MP_AHB5LPENSETR U(0x310) |
| 84 | #define RCC_MP_AHB5LPENCLRR U(0x314) |
| 85 | #define RCC_MP_AHB6LPENSETR U(0x318) |
| 86 | #define RCC_MP_AHB6LPENCLRR U(0x31C) |
| 87 | #define RCC_MP_TZAHB6LPENSETR U(0x320) |
| 88 | #define RCC_MP_TZAHB6LPENCLRR U(0x324) |
| 89 | #define RCC_MC_APB4LPENSETR U(0x380) |
| 90 | #define RCC_MC_APB4LPENCLRR U(0x384) |
| 91 | #define RCC_MC_APB5LPENSETR U(0x388) |
| 92 | #define RCC_MC_APB5LPENCLRR U(0x38C) |
| 93 | #define RCC_MC_AHB5LPENSETR U(0x390) |
| 94 | #define RCC_MC_AHB5LPENCLRR U(0x394) |
| 95 | #define RCC_MC_AHB6LPENSETR U(0x398) |
| 96 | #define RCC_MC_AHB6LPENCLRR U(0x39C) |
| 97 | #define RCC_BR_RSTSCLRR U(0x400) |
| 98 | #define RCC_MP_GRSTCSETR U(0x404) |
| 99 | #define RCC_MP_RSTSCLRR U(0x408) |
| 100 | #define RCC_MP_IWDGFZSETR U(0x40C) |
| 101 | #define RCC_MP_IWDGFZCLRR U(0x410) |
| 102 | #define RCC_MP_CIER U(0x414) |
| 103 | #define RCC_MP_CIFR U(0x418) |
| 104 | #define RCC_PWRLPDLYCR U(0x41C) |
| 105 | #define RCC_MP_RSTSSETR U(0x420) |
| 106 | #define RCC_MCO1CFGR U(0x800) |
| 107 | #define RCC_MCO2CFGR U(0x804) |
| 108 | #define RCC_OCRDYR U(0x808) |
| 109 | #define RCC_DBGCFGR U(0x80C) |
| 110 | #define RCC_RCK3SELR U(0x820) |
| 111 | #define RCC_RCK4SELR U(0x824) |
| 112 | #define RCC_TIMG1PRER U(0x828) |
| 113 | #define RCC_TIMG2PRER U(0x82C) |
| 114 | #define RCC_MCUDIVR U(0x830) |
| 115 | #define RCC_APB1DIVR U(0x834) |
| 116 | #define RCC_APB2DIVR U(0x838) |
| 117 | #define RCC_APB3DIVR U(0x83C) |
| 118 | #define RCC_PLL3CR U(0x880) |
| 119 | #define RCC_PLL3CFGR1 U(0x884) |
| 120 | #define RCC_PLL3CFGR2 U(0x888) |
| 121 | #define RCC_PLL3FRACR U(0x88C) |
| 122 | #define RCC_PLL3CSGR U(0x890) |
| 123 | #define RCC_PLL4CR U(0x894) |
| 124 | #define RCC_PLL4CFGR1 U(0x898) |
| 125 | #define RCC_PLL4CFGR2 U(0x89C) |
| 126 | #define RCC_PLL4FRACR U(0x8A0) |
| 127 | #define RCC_PLL4CSGR U(0x8A4) |
| 128 | #define RCC_I2C12CKSELR U(0x8C0) |
| 129 | #define RCC_I2C35CKSELR U(0x8C4) |
| 130 | #define RCC_SAI1CKSELR U(0x8C8) |
| 131 | #define RCC_SAI2CKSELR U(0x8CC) |
| 132 | #define RCC_SAI3CKSELR U(0x8D0) |
| 133 | #define RCC_SAI4CKSELR U(0x8D4) |
| 134 | #define RCC_SPI2S1CKSELR U(0x8D8) |
| 135 | #define RCC_SPI2S23CKSELR U(0x8DC) |
| 136 | #define RCC_SPI45CKSELR U(0x8E0) |
| 137 | #define RCC_UART6CKSELR U(0x8E4) |
| 138 | #define RCC_UART24CKSELR U(0x8E8) |
| 139 | #define RCC_UART35CKSELR U(0x8EC) |
| 140 | #define RCC_UART78CKSELR U(0x8F0) |
| 141 | #define RCC_SDMMC12CKSELR U(0x8F4) |
| 142 | #define RCC_SDMMC3CKSELR U(0x8F8) |
| 143 | #define RCC_ETHCKSELR U(0x8FC) |
| 144 | #define RCC_QSPICKSELR U(0x900) |
| 145 | #define RCC_FMCCKSELR U(0x904) |
| 146 | #define RCC_FDCANCKSELR U(0x90C) |
| 147 | #define RCC_SPDIFCKSELR U(0x914) |
| 148 | #define RCC_CECCKSELR U(0x918) |
| 149 | #define RCC_USBCKSELR U(0x91C) |
| 150 | #define RCC_RNG2CKSELR U(0x920) |
| 151 | #define RCC_DSICKSELR U(0x924) |
| 152 | #define RCC_ADCCKSELR U(0x928) |
| 153 | #define RCC_LPTIM45CKSELR U(0x92C) |
| 154 | #define RCC_LPTIM23CKSELR U(0x930) |
| 155 | #define RCC_LPTIM1CKSELR U(0x934) |
| 156 | #define RCC_APB1RSTSETR U(0x980) |
| 157 | #define RCC_APB1RSTCLRR U(0x984) |
| 158 | #define RCC_APB2RSTSETR U(0x988) |
| 159 | #define RCC_APB2RSTCLRR U(0x98C) |
| 160 | #define RCC_APB3RSTSETR U(0x990) |
| 161 | #define RCC_APB3RSTCLRR U(0x994) |
| 162 | #define RCC_AHB2RSTSETR U(0x998) |
| 163 | #define RCC_AHB2RSTCLRR U(0x99C) |
| 164 | #define RCC_AHB3RSTSETR U(0x9A0) |
| 165 | #define RCC_AHB3RSTCLRR U(0x9A4) |
| 166 | #define RCC_AHB4RSTSETR U(0x9A8) |
| 167 | #define RCC_AHB4RSTCLRR U(0x9AC) |
| 168 | #define RCC_MP_APB1ENSETR U(0xA00) |
| 169 | #define RCC_MP_APB1ENCLRR U(0xA04) |
| 170 | #define RCC_MP_APB2ENSETR U(0xA08) |
| 171 | #define RCC_MP_APB2ENCLRR U(0xA0C) |
| 172 | #define RCC_MP_APB3ENSETR U(0xA10) |
| 173 | #define RCC_MP_APB3ENCLRR U(0xA14) |
| 174 | #define RCC_MP_AHB2ENSETR U(0xA18) |
| 175 | #define RCC_MP_AHB2ENCLRR U(0xA1C) |
| 176 | #define RCC_MP_AHB3ENSETR U(0xA20) |
| 177 | #define RCC_MP_AHB3ENCLRR U(0xA24) |
| 178 | #define RCC_MP_AHB4ENSETR U(0xA28) |
| 179 | #define RCC_MP_AHB4ENCLRR U(0xA2C) |
| 180 | #define RCC_MP_MLAHBENSETR U(0xA38) |
| 181 | #define RCC_MP_MLAHBENCLRR U(0xA3C) |
| 182 | #define RCC_MC_APB1ENSETR U(0xA80) |
| 183 | #define RCC_MC_APB1ENCLRR U(0xA84) |
| 184 | #define RCC_MC_APB2ENSETR U(0xA88) |
| 185 | #define RCC_MC_APB2ENCLRR U(0xA8C) |
| 186 | #define RCC_MC_APB3ENSETR U(0xA90) |
| 187 | #define RCC_MC_APB3ENCLRR U(0xA94) |
| 188 | #define RCC_MC_AHB2ENSETR U(0xA98) |
| 189 | #define RCC_MC_AHB2ENCLRR U(0xA9C) |
| 190 | #define RCC_MC_AHB3ENSETR U(0xAA0) |
| 191 | #define RCC_MC_AHB3ENCLRR U(0xAA4) |
| 192 | #define RCC_MC_AHB4ENSETR U(0xAA8) |
| 193 | #define RCC_MC_AHB4ENCLRR U(0xAAC) |
| 194 | #define RCC_MC_AXIMENSETR U(0xAB0) |
| 195 | #define RCC_MC_AXIMENCLRR U(0xAB4) |
| 196 | #define RCC_MC_MLAHBENSETR U(0xAB8) |
| 197 | #define RCC_MC_MLAHBENCLRR U(0xABC) |
| 198 | #define RCC_MP_APB1LPENSETR U(0xB00) |
| 199 | #define RCC_MP_APB1LPENCLRR U(0xB04) |
| 200 | #define RCC_MP_APB2LPENSETR U(0xB08) |
| 201 | #define RCC_MP_APB2LPENCLRR U(0xB0C) |
| 202 | #define RCC_MP_APB3LPENSETR U(0xB10) |
| 203 | #define RCC_MP_APB3LPENCLRR U(0xB14) |
| 204 | #define RCC_MP_AHB2LPENSETR U(0xB18) |
| 205 | #define RCC_MP_AHB2LPENCLRR U(0xB1C) |
| 206 | #define RCC_MP_AHB3LPENSETR U(0xB20) |
| 207 | #define RCC_MP_AHB3LPENCLRR U(0xB24) |
| 208 | #define RCC_MP_AHB4LPENSETR U(0xB28) |
| 209 | #define RCC_MP_AHB4LPENCLRR U(0xB2C) |
| 210 | #define RCC_MP_AXIMLPENSETR U(0xB30) |
| 211 | #define RCC_MP_AXIMLPENCLRR U(0xB34) |
| 212 | #define RCC_MP_MLAHBLPENSETR U(0xB38) |
| 213 | #define RCC_MP_MLAHBLPENCLRR U(0xB3C) |
| 214 | #define RCC_MC_APB1LPENSETR U(0xB80) |
| 215 | #define RCC_MC_APB1LPENCLRR U(0xB84) |
| 216 | #define RCC_MC_APB2LPENSETR U(0xB88) |
| 217 | #define RCC_MC_APB2LPENCLRR U(0xB8C) |
| 218 | #define RCC_MC_APB3LPENSETR U(0xB90) |
| 219 | #define RCC_MC_APB3LPENCLRR U(0xB94) |
| 220 | #define RCC_MC_AHB2LPENSETR U(0xB98) |
| 221 | #define RCC_MC_AHB2LPENCLRR U(0xB9C) |
| 222 | #define RCC_MC_AHB3LPENSETR U(0xBA0) |
| 223 | #define RCC_MC_AHB3LPENCLRR U(0xBA4) |
| 224 | #define RCC_MC_AHB4LPENSETR U(0xBA8) |
| 225 | #define RCC_MC_AHB4LPENCLRR U(0xBAC) |
| 226 | #define RCC_MC_AXIMLPENSETR U(0xBB0) |
| 227 | #define RCC_MC_AXIMLPENCLRR U(0xBB4) |
| 228 | #define RCC_MC_MLAHBLPENSETR U(0xBB8) |
| 229 | #define RCC_MC_MLAHBLPENCLRR U(0xBBC) |
| 230 | #define RCC_MC_RSTSCLRR U(0xC00) |
| 231 | #define RCC_MC_CIER U(0xC14) |
| 232 | #define RCC_MC_CIFR U(0xC18) |
| 233 | #define RCC_VERR U(0xFF4) |
| 234 | #define RCC_IDR U(0xFF8) |
| 235 | #define RCC_SIDR U(0xFFC) |
| 236 | |
| 237 | /* RCC_TZCR register fields */ |
| 238 | #define RCC_TZCR_TZEN BIT(0) |
| 239 | #define RCC_TZCR_MCKPROT BIT(1) |
| 240 | |
| 241 | /* RCC_OCENSETR register fields */ |
| 242 | #define RCC_OCENSETR_HSION BIT(0) |
| 243 | #define RCC_OCENSETR_HSIKERON BIT(1) |
| 244 | #define RCC_OCENSETR_CSION BIT(4) |
| 245 | #define RCC_OCENSETR_CSIKERON BIT(5) |
| 246 | #define RCC_OCENSETR_DIGBYP BIT(7) |
| 247 | #define RCC_OCENSETR_HSEON BIT(8) |
| 248 | #define RCC_OCENSETR_HSEKERON BIT(9) |
| 249 | #define RCC_OCENSETR_HSEBYP BIT(10) |
| 250 | #define RCC_OCENSETR_HSECSSON BIT(11) |
| 251 | |
| 252 | /* RCC_OCENCLRR register fields */ |
| 253 | #define RCC_OCENCLRR_HSION BIT(0) |
| 254 | #define RCC_OCENCLRR_HSIKERON BIT(1) |
| 255 | #define RCC_OCENCLRR_CSION BIT(4) |
| 256 | #define RCC_OCENCLRR_CSIKERON BIT(5) |
| 257 | #define RCC_OCENCLRR_DIGBYP BIT(7) |
| 258 | #define RCC_OCENCLRR_HSEON BIT(8) |
| 259 | #define RCC_OCENCLRR_HSEKERON BIT(9) |
| 260 | #define RCC_OCENCLRR_HSEBYP BIT(10) |
| 261 | |
| 262 | /* RCC_HSICFGR register fields */ |
| 263 | #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) |
| 264 | #define RCC_HSICFGR_HSIDIV_SHIFT 0 |
| 265 | #define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8) |
| 266 | #define RCC_HSICFGR_HSITRIM_SHIFT 8 |
| 267 | #define RCC_HSICFGR_HSICAL_MASK GENMASK(24, 16) |
| 268 | #define RCC_HSICFGR_HSICAL_SHIFT 16 |
| 269 | #define RCC_HSICFGR_HSICAL_TEMP_MASK GENMASK(27, 25) |
| 270 | |
| 271 | /* RCC_CSICFGR register fields */ |
| 272 | #define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8) |
| 273 | #define RCC_CSICFGR_CSITRIM_SHIFT 8 |
| 274 | #define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16) |
| 275 | #define RCC_CSICFGR_CSICAL_SHIFT 16 |
| 276 | |
| 277 | /* RCC_MPCKSELR register fields */ |
| 278 | #define RCC_MPCKSELR_HSI 0x00000000 |
| 279 | #define RCC_MPCKSELR_HSE 0x00000001 |
| 280 | #define RCC_MPCKSELR_PLL 0x00000002 |
| 281 | #define RCC_MPCKSELR_PLL_MPUDIV 0x00000003 |
| 282 | #define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0) |
| 283 | #define RCC_MPCKSELR_MPUSRC_SHIFT 0 |
| 284 | #define RCC_MPCKSELR_MPUSRCRDY BIT(31) |
| 285 | |
| 286 | /* RCC_ASSCKSELR register fields */ |
| 287 | #define RCC_ASSCKSELR_HSI 0x00000000 |
| 288 | #define RCC_ASSCKSELR_HSE 0x00000001 |
| 289 | #define RCC_ASSCKSELR_PLL 0x00000002 |
| 290 | #define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0) |
| 291 | #define RCC_ASSCKSELR_AXISSRC_SHIFT 0 |
| 292 | #define RCC_ASSCKSELR_AXISSRCRDY BIT(31) |
| 293 | |
| 294 | /* RCC_RCK12SELR register fields */ |
| 295 | #define RCC_RCK12SELR_PLL12SRC_MASK GENMASK(1, 0) |
| 296 | #define RCC_RCK12SELR_PLL12SRC_SHIFT 0 |
| 297 | #define RCC_RCK12SELR_PLL12SRCRDY BIT(31) |
| 298 | |
| 299 | /* RCC_MPCKDIVR register fields */ |
| 300 | #define RCC_MPCKDIVR_MPUDIV_MASK GENMASK(2, 0) |
| 301 | #define RCC_MPCKDIVR_MPUDIV_SHIFT 0 |
| 302 | #define RCC_MPCKDIVR_MPUDIVRDY BIT(31) |
| 303 | |
| 304 | /* RCC_AXIDIVR register fields */ |
| 305 | #define RCC_AXIDIVR_AXIDIV_MASK GENMASK(2, 0) |
| 306 | #define RCC_AXIDIVR_AXIDIV_SHIFT 0 |
| 307 | #define RCC_AXIDIVR_AXIDIVRDY BIT(31) |
| 308 | |
| 309 | /* RCC_APB4DIVR register fields */ |
| 310 | #define RCC_APB4DIVR_APB4DIV_MASK GENMASK(2, 0) |
| 311 | #define RCC_APB4DIVR_APB4DIV_SHIFT 0 |
| 312 | #define RCC_APB4DIVR_APB4DIVRDY BIT(31) |
| 313 | |
| 314 | /* RCC_APB5DIVR register fields */ |
| 315 | #define RCC_APB5DIVR_APB5DIV_MASK GENMASK(2, 0) |
| 316 | #define RCC_APB5DIVR_APB5DIV_SHIFT 0 |
| 317 | #define RCC_APB5DIVR_APB5DIVRDY BIT(31) |
| 318 | |
| 319 | /* RCC_RTCDIVR register fields */ |
| 320 | #define RCC_RTCDIVR_RTCDIV_MASK GENMASK(5, 0) |
| 321 | #define RCC_RTCDIVR_RTCDIV_SHIFT 0 |
| 322 | |
| 323 | /* RCC_MSSCKSELR register fields */ |
| 324 | #define RCC_MSSCKSELR_HSI 0x00000000 |
| 325 | #define RCC_MSSCKSELR_HSE 0x00000001 |
| 326 | #define RCC_MSSCKSELR_CSI 0x00000002 |
| 327 | #define RCC_MSSCKSELR_PLL 0x00000003 |
| 328 | #define RCC_MSSCKSELR_MCUSSRC_MASK GENMASK(1, 0) |
| 329 | #define RCC_MSSCKSELR_MCUSSRC_SHIFT 0 |
| 330 | #define RCC_MSSCKSELR_MCUSSRCRDY BIT(31) |
| 331 | |
| 332 | /* RCC_PLL1CR register fields */ |
| 333 | #define RCC_PLL1CR_PLLON BIT(0) |
| 334 | #define RCC_PLL1CR_PLL1RDY BIT(1) |
| 335 | #define RCC_PLL1CR_SSCG_CTRL BIT(2) |
| 336 | #define RCC_PLL1CR_DIVPEN BIT(4) |
| 337 | #define RCC_PLL1CR_DIVQEN BIT(5) |
| 338 | #define RCC_PLL1CR_DIVREN BIT(6) |
| 339 | |
| 340 | /* RCC_PLL1CFGR1 register fields */ |
| 341 | #define RCC_PLL1CFGR1_DIVN_MASK GENMASK(8, 0) |
| 342 | #define RCC_PLL1CFGR1_DIVN_SHIFT 0 |
| 343 | #define RCC_PLL1CFGR1_DIVM1_MASK GENMASK(21, 16) |
| 344 | #define RCC_PLL1CFGR1_DIVM1_SHIFT 16 |
| 345 | |
| 346 | /* RCC_PLL1CFGR2 register fields */ |
| 347 | #define RCC_PLL1CFGR2_DIVP_MASK GENMASK(6, 0) |
| 348 | #define RCC_PLL1CFGR2_DIVP_SHIFT 0 |
| 349 | #define RCC_PLL1CFGR2_DIVQ_MASK GENMASK(14, 8) |
| 350 | #define RCC_PLL1CFGR2_DIVQ_SHIFT 8 |
| 351 | #define RCC_PLL1CFGR2_DIVR_MASK GENMASK(22, 16) |
| 352 | #define RCC_PLL1CFGR2_DIVR_SHIFT 16 |
| 353 | |
| 354 | /* RCC_PLL1FRACR register fields */ |
| 355 | #define RCC_PLL1FRACR_FRACV_MASK GENMASK(15, 3) |
| 356 | #define RCC_PLL1FRACR_FRACV_SHIFT 3 |
| 357 | #define RCC_PLL1FRACR_FRACLE BIT(16) |
| 358 | |
| 359 | /* RCC_PLL1CSGR register fields */ |
| 360 | #define RCC_PLL1CSGR_MOD_PER_MASK GENMASK(12, 0) |
| 361 | #define RCC_PLL1CSGR_MOD_PER_SHIFT 0 |
| 362 | #define RCC_PLL1CSGR_TPDFN_DIS BIT(13) |
| 363 | #define RCC_PLL1CSGR_RPDFN_DIS BIT(14) |
| 364 | #define RCC_PLL1CSGR_SSCG_MODE BIT(15) |
| 365 | #define RCC_PLL1CSGR_INC_STEP_MASK GENMASK(30, 16) |
| 366 | #define RCC_PLL1CSGR_INC_STEP_SHIFT 16 |
| 367 | |
| 368 | /* RCC_PLL2CR register fields */ |
| 369 | #define RCC_PLL2CR_PLLON BIT(0) |
| 370 | #define RCC_PLL2CR_PLL2RDY BIT(1) |
| 371 | #define RCC_PLL2CR_SSCG_CTRL BIT(2) |
| 372 | #define RCC_PLL2CR_DIVPEN BIT(4) |
| 373 | #define RCC_PLL2CR_DIVQEN BIT(5) |
| 374 | #define RCC_PLL2CR_DIVREN BIT(6) |
| 375 | |
| 376 | /* RCC_PLL2CFGR1 register fields */ |
| 377 | #define RCC_PLL2CFGR1_DIVN_MASK GENMASK(8, 0) |
| 378 | #define RCC_PLL2CFGR1_DIVN_SHIFT 0 |
| 379 | #define RCC_PLL2CFGR1_DIVM2_MASK GENMASK(21, 16) |
| 380 | #define RCC_PLL2CFGR1_DIVM2_SHIFT 16 |
| 381 | |
| 382 | /* RCC_PLL2CFGR2 register fields */ |
| 383 | #define RCC_PLL2CFGR2_DIVP_MASK GENMASK(6, 0) |
| 384 | #define RCC_PLL2CFGR2_DIVP_SHIFT 0 |
| 385 | #define RCC_PLL2CFGR2_DIVQ_MASK GENMASK(14, 8) |
| 386 | #define RCC_PLL2CFGR2_DIVQ_SHIFT 8 |
| 387 | #define RCC_PLL2CFGR2_DIVR_MASK GENMASK(22, 16) |
| 388 | #define RCC_PLL2CFGR2_DIVR_SHIFT 16 |
| 389 | |
| 390 | /* RCC_PLL2FRACR register fields */ |
| 391 | #define RCC_PLL2FRACR_FRACV_MASK GENMASK(15, 3) |
| 392 | #define RCC_PLL2FRACR_FRACV_SHIFT 3 |
| 393 | #define RCC_PLL2FRACR_FRACLE BIT(16) |
| 394 | |
| 395 | /* RCC_PLL2CSGR register fields */ |
| 396 | #define RCC_PLL2CSGR_MOD_PER_MASK GENMASK(12, 0) |
| 397 | #define RCC_PLL2CSGR_MOD_PER_SHIFT 0 |
| 398 | #define RCC_PLL2CSGR_TPDFN_DIS BIT(13) |
| 399 | #define RCC_PLL2CSGR_RPDFN_DIS BIT(14) |
| 400 | #define RCC_PLL2CSGR_SSCG_MODE BIT(15) |
| 401 | #define RCC_PLL2CSGR_INC_STEP_MASK GENMASK(30, 16) |
| 402 | #define RCC_PLL2CSGR_INC_STEP_SHIFT 16 |
| 403 | |
| 404 | /* RCC_I2C46CKSELR register fields */ |
| 405 | #define RCC_I2C46CKSELR_I2C46SRC_MASK GENMASK(2, 0) |
| 406 | #define RCC_I2C46CKSELR_I2C46SRC_SHIFT 0 |
| 407 | |
| 408 | /* RCC_SPI6CKSELR register fields */ |
| 409 | #define RCC_SPI6CKSELR_SPI6SRC_MASK GENMASK(2, 0) |
| 410 | #define RCC_SPI6CKSELR_SPI6SRC_SHIFT 0 |
| 411 | |
| 412 | /* RCC_UART1CKSELR register fields */ |
| 413 | #define RCC_UART1CKSELR_UART1SRC_MASK GENMASK(2, 0) |
| 414 | #define RCC_UART1CKSELR_UART1SRC_SHIFT 0 |
| 415 | |
| 416 | /* RCC_RNG1CKSELR register fields */ |
| 417 | #define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0) |
| 418 | #define RCC_RNG1CKSELR_RNG1SRC_SHIFT 0 |
| 419 | |
| 420 | /* RCC_CPERCKSELR register fields */ |
| 421 | #define RCC_CPERCKSELR_HSI 0x00000000 |
| 422 | #define RCC_CPERCKSELR_CSI 0x00000001 |
| 423 | #define RCC_CPERCKSELR_HSE 0x00000002 |
| 424 | #define RCC_CPERCKSELR_CKPERSRC_MASK GENMASK(1, 0) |
| 425 | #define RCC_CPERCKSELR_CKPERSRC_SHIFT 0 |
| 426 | |
| 427 | /* RCC_STGENCKSELR register fields */ |
| 428 | #define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0) |
| 429 | #define RCC_STGENCKSELR_STGENSRC_SHIFT 0 |
| 430 | |
| 431 | /* RCC_DDRITFCR register fields */ |
| 432 | #define RCC_DDRITFCR_DDRC1EN BIT(0) |
| 433 | #define RCC_DDRITFCR_DDRC1LPEN BIT(1) |
| 434 | #define RCC_DDRITFCR_DDRC2EN BIT(2) |
| 435 | #define RCC_DDRITFCR_DDRC2LPEN BIT(3) |
| 436 | #define RCC_DDRITFCR_DDRPHYCEN BIT(4) |
| 437 | #define RCC_DDRITFCR_DDRPHYCLPEN BIT(5) |
| 438 | #define RCC_DDRITFCR_DDRCAPBEN BIT(6) |
| 439 | #define RCC_DDRITFCR_DDRCAPBLPEN BIT(7) |
| 440 | #define RCC_DDRITFCR_AXIDCGEN BIT(8) |
| 441 | #define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9) |
| 442 | #define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10) |
| 443 | #define RCC_DDRITFCR_KERDCG_DLY_MASK GENMASK(13, 11) |
| 444 | #define RCC_DDRITFCR_KERDCG_DLY_SHIFT 11 |
| 445 | #define RCC_DDRITFCR_DDRCAPBRST BIT(14) |
| 446 | #define RCC_DDRITFCR_DDRCAXIRST BIT(15) |
| 447 | #define RCC_DDRITFCR_DDRCORERST BIT(16) |
| 448 | #define RCC_DDRITFCR_DPHYAPBRST BIT(17) |
| 449 | #define RCC_DDRITFCR_DPHYRST BIT(18) |
| 450 | #define RCC_DDRITFCR_DPHYCTLRST BIT(19) |
| 451 | #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) |
| 452 | #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 |
| 453 | #define RCC_DDRITFCR_DDRCKMOD_SSR 0 |
| 454 | #define RCC_DDRITFCR_DDRCKMOD_ASR1 BIT(20) |
| 455 | #define RCC_DDRITFCR_DDRCKMOD_HSR1 BIT(21) |
| 456 | #define RCC_DDRITFCR_GSKPMOD BIT(23) |
| 457 | #define RCC_DDRITFCR_GSKPCTRL BIT(24) |
| 458 | #define RCC_DDRITFCR_DFILP_WIDTH_MASK GENMASK(27, 25) |
| 459 | #define RCC_DDRITFCR_DFILP_WIDTH_SHIFT 25 |
| 460 | #define RCC_DDRITFCR_GSKP_DUR_MASK GENMASK(31, 28) |
| 461 | #define RCC_DDRITFCR_GSKP_DUR_SHIFT 28 |
| 462 | |
| 463 | /* RCC_MP_BOOTCR register fields */ |
| 464 | #define RCC_MP_BOOTCR_MCU_BEN BIT(0) |
| 465 | #define RCC_MP_BOOTCR_MPU_BEN BIT(1) |
| 466 | |
| 467 | /* RCC_MP_SREQSETR register fields */ |
| 468 | #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0) |
| 469 | #define RCC_MP_SREQSETR_STPREQ_P1 BIT(1) |
| 470 | |
| 471 | /* RCC_MP_SREQCLRR register fields */ |
| 472 | #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0) |
| 473 | #define RCC_MP_SREQCLRR_STPREQ_P1 BIT(1) |
| 474 | |
| 475 | /* RCC_MP_GCR register fields */ |
| 476 | #define RCC_MP_GCR_BOOT_MCU BIT(0) |
| 477 | |
| 478 | /* RCC_MP_APRSTCR register fields */ |
| 479 | #define RCC_MP_APRSTCR_RDCTLEN BIT(0) |
| 480 | #define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8) |
| 481 | #define RCC_MP_APRSTCR_RSTTO_SHIFT 8 |
| 482 | |
| 483 | /* RCC_MP_APRSTSR register fields */ |
| 484 | #define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8) |
| 485 | #define RCC_MP_APRSTSR_RSTTOV_SHIFT 8 |
| 486 | |
| 487 | /* RCC_BDCR register fields */ |
| 488 | #define RCC_BDCR_LSEON BIT(0) |
| 489 | #define RCC_BDCR_LSEBYP BIT(1) |
| 490 | #define RCC_BDCR_LSERDY BIT(2) |
| 491 | #define RCC_BDCR_DIGBYP BIT(3) |
| 492 | #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) |
| 493 | #define RCC_BDCR_LSEDRV_SHIFT 4 |
| 494 | #define RCC_BDCR_LSECSSON BIT(8) |
| 495 | #define RCC_BDCR_LSECSSD BIT(9) |
| 496 | #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) |
| 497 | #define RCC_BDCR_RTCSRC_SHIFT 16 |
| 498 | #define RCC_BDCR_RTCCKEN BIT(20) |
| 499 | #define RCC_BDCR_VSWRST BIT(31) |
| 500 | |
| 501 | /* RCC_RDLSICR register fields */ |
| 502 | #define RCC_RDLSICR_LSION BIT(0) |
| 503 | #define RCC_RDLSICR_LSIRDY BIT(1) |
| 504 | #define RCC_RDLSICR_MRD_MASK GENMASK(20, 16) |
| 505 | #define RCC_RDLSICR_MRD_SHIFT 16 |
| 506 | #define RCC_RDLSICR_EADLY_MASK GENMASK(26, 24) |
| 507 | #define RCC_RDLSICR_EADLY_SHIFT 24 |
| 508 | #define RCC_RDLSICR_SPARE_MASK GENMASK(31, 27) |
| 509 | #define RCC_RDLSICR_SPARE_SHIFT 27 |
| 510 | |
| 511 | /* RCC_APB4RSTSETR register fields */ |
| 512 | #define RCC_APB4RSTSETR_LTDCRST BIT(0) |
| 513 | #define RCC_APB4RSTSETR_DSIRST BIT(4) |
| 514 | #define RCC_APB4RSTSETR_DDRPERFMRST BIT(8) |
| 515 | #define RCC_APB4RSTSETR_USBPHYRST BIT(16) |
| 516 | |
| 517 | /* RCC_APB4RSTCLRR register fields */ |
| 518 | #define RCC_APB4RSTCLRR_LTDCRST BIT(0) |
| 519 | #define RCC_APB4RSTCLRR_DSIRST BIT(4) |
| 520 | #define RCC_APB4RSTCLRR_DDRPERFMRST BIT(8) |
| 521 | #define RCC_APB4RSTCLRR_USBPHYRST BIT(16) |
| 522 | |
| 523 | /* RCC_APB5RSTSETR register fields */ |
| 524 | #define RCC_APB5RSTSETR_SPI6RST BIT(0) |
| 525 | #define RCC_APB5RSTSETR_I2C4RST BIT(2) |
| 526 | #define RCC_APB5RSTSETR_I2C6RST BIT(3) |
| 527 | #define RCC_APB5RSTSETR_USART1RST BIT(4) |
| 528 | #define RCC_APB5RSTSETR_STGENRST BIT(20) |
| 529 | |
| 530 | /* RCC_APB5RSTCLRR register fields */ |
| 531 | #define RCC_APB5RSTCLRR_SPI6RST BIT(0) |
| 532 | #define RCC_APB5RSTCLRR_I2C4RST BIT(2) |
| 533 | #define RCC_APB5RSTCLRR_I2C6RST BIT(3) |
| 534 | #define RCC_APB5RSTCLRR_USART1RST BIT(4) |
| 535 | #define RCC_APB5RSTCLRR_STGENRST BIT(20) |
| 536 | |
| 537 | /* RCC_AHB5RSTSETR register fields */ |
| 538 | #define RCC_AHB5RSTSETR_GPIOZRST BIT(0) |
| 539 | #define RCC_AHB5RSTSETR_CRYP1RST BIT(4) |
| 540 | #define RCC_AHB5RSTSETR_HASH1RST BIT(5) |
| 541 | #define RCC_AHB5RSTSETR_RNG1RST BIT(6) |
| 542 | #define RCC_AHB5RSTSETR_AXIMCRST BIT(16) |
| 543 | |
| 544 | /* RCC_AHB5RSTCLRR register fields */ |
| 545 | #define RCC_AHB5RSTCLRR_GPIOZRST BIT(0) |
| 546 | #define RCC_AHB5RSTCLRR_CRYP1RST BIT(4) |
| 547 | #define RCC_AHB5RSTCLRR_HASH1RST BIT(5) |
| 548 | #define RCC_AHB5RSTCLRR_RNG1RST BIT(6) |
| 549 | #define RCC_AHB5RSTCLRR_AXIMCRST BIT(16) |
| 550 | |
| 551 | /* RCC_AHB6RSTSETR register fields */ |
| 552 | #define RCC_AHB6RSTSETR_GPURST BIT(5) |
| 553 | #define RCC_AHB6RSTSETR_ETHMACRST BIT(10) |
| 554 | #define RCC_AHB6RSTSETR_FMCRST BIT(12) |
| 555 | #define RCC_AHB6RSTSETR_QSPIRST BIT(14) |
| 556 | #define RCC_AHB6RSTSETR_SDMMC1RST BIT(16) |
| 557 | #define RCC_AHB6RSTSETR_SDMMC2RST BIT(17) |
| 558 | #define RCC_AHB6RSTSETR_CRC1RST BIT(20) |
| 559 | #define RCC_AHB6RSTSETR_USBHRST BIT(24) |
| 560 | |
| 561 | /* RCC_AHB6RSTCLRR register fields */ |
| 562 | #define RCC_AHB6RSTCLRR_ETHMACRST BIT(10) |
| 563 | #define RCC_AHB6RSTCLRR_FMCRST BIT(12) |
| 564 | #define RCC_AHB6RSTCLRR_QSPIRST BIT(14) |
| 565 | #define RCC_AHB6RSTCLRR_SDMMC1RST BIT(16) |
| 566 | #define RCC_AHB6RSTCLRR_SDMMC2RST BIT(17) |
| 567 | #define RCC_AHB6RSTCLRR_CRC1RST BIT(20) |
| 568 | #define RCC_AHB6RSTCLRR_USBHRST BIT(24) |
| 569 | |
| 570 | /* RCC_TZAHB6RSTSETR register fields */ |
| 571 | #define RCC_TZAHB6RSTSETR_MDMARST BIT(0) |
| 572 | |
| 573 | /* RCC_TZAHB6RSTCLRR register fields */ |
| 574 | #define RCC_TZAHB6RSTCLRR_MDMARST BIT(0) |
| 575 | |
| 576 | /* RCC_MP_APB4ENSETR register fields */ |
| 577 | #define RCC_MP_APB4ENSETR_LTDCEN BIT(0) |
| 578 | #define RCC_MP_APB4ENSETR_DSIEN BIT(4) |
| 579 | #define RCC_MP_APB4ENSETR_DDRPERFMEN BIT(8) |
| 580 | #define RCC_MP_APB4ENSETR_IWDG2APBEN BIT(15) |
| 581 | #define RCC_MP_APB4ENSETR_USBPHYEN BIT(16) |
| 582 | #define RCC_MP_APB4ENSETR_STGENROEN BIT(20) |
| 583 | |
| 584 | /* RCC_MP_APB4ENCLRR register fields */ |
| 585 | #define RCC_MP_APB4ENCLRR_LTDCEN BIT(0) |
| 586 | #define RCC_MP_APB4ENCLRR_DSIEN BIT(4) |
| 587 | #define RCC_MP_APB4ENCLRR_DDRPERFMEN BIT(8) |
| 588 | #define RCC_MP_APB4ENCLRR_IWDG2APBEN BIT(15) |
| 589 | #define RCC_MP_APB4ENCLRR_USBPHYEN BIT(16) |
| 590 | #define RCC_MP_APB4ENCLRR_STGENROEN BIT(20) |
| 591 | |
| 592 | /* RCC_MP_APB5ENSETR register fields */ |
| 593 | #define RCC_MP_APB5ENSETR_SPI6EN BIT(0) |
| 594 | #define RCC_MP_APB5ENSETR_I2C4EN BIT(2) |
| 595 | #define RCC_MP_APB5ENSETR_I2C6EN BIT(3) |
| 596 | #define RCC_MP_APB5ENSETR_USART1EN BIT(4) |
| 597 | #define RCC_MP_APB5ENSETR_RTCAPBEN BIT(8) |
| 598 | #define RCC_MP_APB5ENSETR_TZC1EN BIT(11) |
| 599 | #define RCC_MP_APB5ENSETR_TZC2EN BIT(12) |
| 600 | #define RCC_MP_APB5ENSETR_TZPCEN BIT(13) |
| 601 | #define RCC_MP_APB5ENSETR_IWDG1APBEN BIT(15) |
| 602 | #define RCC_MP_APB5ENSETR_BSECEN BIT(16) |
| 603 | #define RCC_MP_APB5ENSETR_STGENEN BIT(20) |
| 604 | |
| 605 | /* RCC_MP_APB5ENCLRR register fields */ |
| 606 | #define RCC_MP_APB5ENCLRR_SPI6EN BIT(0) |
| 607 | #define RCC_MP_APB5ENCLRR_I2C4EN BIT(2) |
| 608 | #define RCC_MP_APB5ENCLRR_I2C6EN BIT(3) |
| 609 | #define RCC_MP_APB5ENCLRR_USART1EN BIT(4) |
| 610 | #define RCC_MP_APB5ENCLRR_RTCAPBEN BIT(8) |
| 611 | #define RCC_MP_APB5ENCLRR_TZC1EN BIT(11) |
| 612 | #define RCC_MP_APB5ENCLRR_TZC2EN BIT(12) |
| 613 | #define RCC_MP_APB5ENCLRR_TZPCEN BIT(13) |
| 614 | #define RCC_MP_APB5ENCLRR_IWDG1APBEN BIT(15) |
| 615 | #define RCC_MP_APB5ENCLRR_BSECEN BIT(16) |
| 616 | #define RCC_MP_APB5ENCLRR_STGENEN BIT(20) |
| 617 | |
| 618 | /* RCC_MP_AHB5ENSETR register fields */ |
| 619 | #define RCC_MP_AHB5ENSETR_GPIOZEN BIT(0) |
| 620 | #define RCC_MP_AHB5ENSETR_CRYP1EN BIT(4) |
| 621 | #define RCC_MP_AHB5ENSETR_HASH1EN BIT(5) |
| 622 | #define RCC_MP_AHB5ENSETR_RNG1EN BIT(6) |
| 623 | #define RCC_MP_AHB5ENSETR_BKPSRAMEN BIT(8) |
| 624 | #define RCC_MP_AHB5ENSETR_AXIMCEN BIT(16) |
| 625 | |
| 626 | /* RCC_MP_AHB5ENCLRR register fields */ |
| 627 | #define RCC_MP_AHB5ENCLRR_GPIOZEN BIT(0) |
| 628 | #define RCC_MP_AHB5ENCLRR_CRYP1EN BIT(4) |
| 629 | #define RCC_MP_AHB5ENCLRR_HASH1EN BIT(5) |
| 630 | #define RCC_MP_AHB5ENCLRR_RNG1EN BIT(6) |
| 631 | #define RCC_MP_AHB5ENCLRR_BKPSRAMEN BIT(8) |
| 632 | #define RCC_MP_AHB5ENCLRR_AXIMCEN BIT(16) |
| 633 | |
| 634 | /* RCC_MP_AHB6ENSETR register fields */ |
| 635 | #define RCC_MP_AHB6ENSETR_MDMAEN BIT(0) |
| 636 | #define RCC_MP_AHB6ENSETR_GPUEN BIT(5) |
| 637 | #define RCC_MP_AHB6ENSETR_ETHCKEN BIT(7) |
| 638 | #define RCC_MP_AHB6ENSETR_ETHTXEN BIT(8) |
| 639 | #define RCC_MP_AHB6ENSETR_ETHRXEN BIT(9) |
| 640 | #define RCC_MP_AHB6ENSETR_ETHMACEN BIT(10) |
| 641 | #define RCC_MP_AHB6ENSETR_FMCEN BIT(12) |
| 642 | #define RCC_MP_AHB6ENSETR_QSPIEN BIT(14) |
| 643 | #define RCC_MP_AHB6ENSETR_SDMMC1EN BIT(16) |
| 644 | #define RCC_MP_AHB6ENSETR_SDMMC2EN BIT(17) |
| 645 | #define RCC_MP_AHB6ENSETR_CRC1EN BIT(20) |
| 646 | #define RCC_MP_AHB6ENSETR_USBHEN BIT(24) |
| 647 | |
| 648 | /* RCC_MP_AHB6ENCLRR register fields */ |
| 649 | #define RCC_MP_AHB6ENCLRR_MDMAEN BIT(0) |
| 650 | #define RCC_MP_AHB6ENCLRR_GPUEN BIT(5) |
| 651 | #define RCC_MP_AHB6ENCLRR_ETHCKEN BIT(7) |
| 652 | #define RCC_MP_AHB6ENCLRR_ETHTXEN BIT(8) |
| 653 | #define RCC_MP_AHB6ENCLRR_ETHRXEN BIT(9) |
| 654 | #define RCC_MP_AHB6ENCLRR_ETHMACEN BIT(10) |
| 655 | #define RCC_MP_AHB6ENCLRR_FMCEN BIT(12) |
| 656 | #define RCC_MP_AHB6ENCLRR_QSPIEN BIT(14) |
| 657 | #define RCC_MP_AHB6ENCLRR_SDMMC1EN BIT(16) |
| 658 | #define RCC_MP_AHB6ENCLRR_SDMMC2EN BIT(17) |
| 659 | #define RCC_MP_AHB6ENCLRR_CRC1EN BIT(20) |
| 660 | #define RCC_MP_AHB6ENCLRR_USBHEN BIT(24) |
| 661 | |
| 662 | /* RCC_MP_TZAHB6ENSETR register fields */ |
| 663 | #define RCC_MP_TZAHB6ENSETR_MDMAEN BIT(0) |
| 664 | |
| 665 | /* RCC_MP_TZAHB6ENCLRR register fields */ |
| 666 | #define RCC_MP_TZAHB6ENCLRR_MDMAEN BIT(0) |
| 667 | |
| 668 | /* RCC_MC_APB4ENSETR register fields */ |
| 669 | #define RCC_MC_APB4ENSETR_LTDCEN BIT(0) |
| 670 | #define RCC_MC_APB4ENSETR_DSIEN BIT(4) |
| 671 | #define RCC_MC_APB4ENSETR_DDRPERFMEN BIT(8) |
| 672 | #define RCC_MC_APB4ENSETR_USBPHYEN BIT(16) |
| 673 | #define RCC_MC_APB4ENSETR_STGENROEN BIT(20) |
| 674 | |
| 675 | /* RCC_MC_APB4ENCLRR register fields */ |
| 676 | #define RCC_MC_APB4ENCLRR_LTDCEN BIT(0) |
| 677 | #define RCC_MC_APB4ENCLRR_DSIEN BIT(4) |
| 678 | #define RCC_MC_APB4ENCLRR_DDRPERFMEN BIT(8) |
| 679 | #define RCC_MC_APB4ENCLRR_USBPHYEN BIT(16) |
| 680 | #define RCC_MC_APB4ENCLRR_STGENROEN BIT(20) |
| 681 | |
| 682 | /* RCC_MC_APB5ENSETR register fields */ |
| 683 | #define RCC_MC_APB5ENSETR_SPI6EN BIT(0) |
| 684 | #define RCC_MC_APB5ENSETR_I2C4EN BIT(2) |
| 685 | #define RCC_MC_APB5ENSETR_I2C6EN BIT(3) |
| 686 | #define RCC_MC_APB5ENSETR_USART1EN BIT(4) |
| 687 | #define RCC_MC_APB5ENSETR_RTCAPBEN BIT(8) |
| 688 | #define RCC_MC_APB5ENSETR_TZC1EN BIT(11) |
| 689 | #define RCC_MC_APB5ENSETR_TZC2EN BIT(12) |
| 690 | #define RCC_MC_APB5ENSETR_TZPCEN BIT(13) |
| 691 | #define RCC_MC_APB5ENSETR_BSECEN BIT(16) |
| 692 | #define RCC_MC_APB5ENSETR_STGENEN BIT(20) |
| 693 | |
| 694 | /* RCC_MC_APB5ENCLRR register fields */ |
| 695 | #define RCC_MC_APB5ENCLRR_SPI6EN BIT(0) |
| 696 | #define RCC_MC_APB5ENCLRR_I2C4EN BIT(2) |
| 697 | #define RCC_MC_APB5ENCLRR_I2C6EN BIT(3) |
| 698 | #define RCC_MC_APB5ENCLRR_USART1EN BIT(4) |
| 699 | #define RCC_MC_APB5ENCLRR_RTCAPBEN BIT(8) |
| 700 | #define RCC_MC_APB5ENCLRR_TZC1EN BIT(11) |
| 701 | #define RCC_MC_APB5ENCLRR_TZC2EN BIT(12) |
| 702 | #define RCC_MC_APB5ENCLRR_TZPCEN BIT(13) |
| 703 | #define RCC_MC_APB5ENCLRR_BSECEN BIT(16) |
| 704 | #define RCC_MC_APB5ENCLRR_STGENEN BIT(20) |
| 705 | |
| 706 | /* RCC_MC_AHB5ENSETR register fields */ |
| 707 | #define RCC_MC_AHB5ENSETR_GPIOZEN BIT(0) |
| 708 | #define RCC_MC_AHB5ENSETR_CRYP1EN BIT(4) |
| 709 | #define RCC_MC_AHB5ENSETR_HASH1EN BIT(5) |
| 710 | #define RCC_MC_AHB5ENSETR_RNG1EN BIT(6) |
| 711 | #define RCC_MC_AHB5ENSETR_BKPSRAMEN BIT(8) |
| 712 | |
| 713 | /* RCC_MC_AHB5ENCLRR register fields */ |
| 714 | #define RCC_MC_AHB5ENCLRR_GPIOZEN BIT(0) |
| 715 | #define RCC_MC_AHB5ENCLRR_CRYP1EN BIT(4) |
| 716 | #define RCC_MC_AHB5ENCLRR_HASH1EN BIT(5) |
| 717 | #define RCC_MC_AHB5ENCLRR_RNG1EN BIT(6) |
| 718 | #define RCC_MC_AHB5ENCLRR_BKPSRAMEN BIT(8) |
| 719 | |
| 720 | /* RCC_MC_AHB6ENSETR register fields */ |
| 721 | #define RCC_MC_AHB6ENSETR_MDMAEN BIT(0) |
| 722 | #define RCC_MC_AHB6ENSETR_GPUEN BIT(5) |
| 723 | #define RCC_MC_AHB6ENSETR_ETHCKEN BIT(7) |
| 724 | #define RCC_MC_AHB6ENSETR_ETHTXEN BIT(8) |
| 725 | #define RCC_MC_AHB6ENSETR_ETHRXEN BIT(9) |
| 726 | #define RCC_MC_AHB6ENSETR_ETHMACEN BIT(10) |
| 727 | #define RCC_MC_AHB6ENSETR_FMCEN BIT(12) |
| 728 | #define RCC_MC_AHB6ENSETR_QSPIEN BIT(14) |
| 729 | #define RCC_MC_AHB6ENSETR_SDMMC1EN BIT(16) |
| 730 | #define RCC_MC_AHB6ENSETR_SDMMC2EN BIT(17) |
| 731 | #define RCC_MC_AHB6ENSETR_CRC1EN BIT(20) |
| 732 | #define RCC_MC_AHB6ENSETR_USBHEN BIT(24) |
| 733 | |
| 734 | /* RCC_MC_AHB6ENCLRR register fields */ |
| 735 | #define RCC_MC_AHB6ENCLRR_MDMAEN BIT(0) |
| 736 | #define RCC_MC_AHB6ENCLRR_GPUEN BIT(5) |
| 737 | #define RCC_MC_AHB6ENCLRR_ETHCKEN BIT(7) |
| 738 | #define RCC_MC_AHB6ENCLRR_ETHTXEN BIT(8) |
| 739 | #define RCC_MC_AHB6ENCLRR_ETHRXEN BIT(9) |
| 740 | #define RCC_MC_AHB6ENCLRR_ETHMACEN BIT(10) |
| 741 | #define RCC_MC_AHB6ENCLRR_FMCEN BIT(12) |
| 742 | #define RCC_MC_AHB6ENCLRR_QSPIEN BIT(14) |
| 743 | #define RCC_MC_AHB6ENCLRR_SDMMC1EN BIT(16) |
| 744 | #define RCC_MC_AHB6ENCLRR_SDMMC2EN BIT(17) |
| 745 | #define RCC_MC_AHB6ENCLRR_CRC1EN BIT(20) |
| 746 | #define RCC_MC_AHB6ENCLRR_USBHEN BIT(24) |
| 747 | |
| 748 | /* RCC_MP_APB4LPENSETR register fields */ |
| 749 | #define RCC_MP_APB4LPENSETR_LTDCLPEN BIT(0) |
| 750 | #define RCC_MP_APB4LPENSETR_DSILPEN BIT(4) |
| 751 | #define RCC_MP_APB4LPENSETR_DDRPERFMLPEN BIT(8) |
| 752 | #define RCC_MP_APB4LPENSETR_IWDG2APBLPEN BIT(15) |
| 753 | #define RCC_MP_APB4LPENSETR_USBPHYLPEN BIT(16) |
| 754 | #define RCC_MP_APB4LPENSETR_STGENROLPEN BIT(20) |
| 755 | #define RCC_MP_APB4LPENSETR_STGENROSTPEN BIT(21) |
| 756 | |
| 757 | /* RCC_MP_APB4LPENCLRR register fields */ |
| 758 | #define RCC_MP_APB4LPENCLRR_LTDCLPEN BIT(0) |
| 759 | #define RCC_MP_APB4LPENCLRR_DSILPEN BIT(4) |
| 760 | #define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN BIT(8) |
| 761 | #define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN BIT(15) |
| 762 | #define RCC_MP_APB4LPENCLRR_USBPHYLPEN BIT(16) |
| 763 | #define RCC_MP_APB4LPENCLRR_STGENROLPEN BIT(20) |
| 764 | #define RCC_MP_APB4LPENCLRR_STGENROSTPEN BIT(21) |
| 765 | |
| 766 | /* RCC_MP_APB5LPENSETR register fields */ |
| 767 | #define RCC_MP_APB5LPENSETR_SPI6LPEN BIT(0) |
| 768 | #define RCC_MP_APB5LPENSETR_I2C4LPEN BIT(2) |
| 769 | #define RCC_MP_APB5LPENSETR_I2C6LPEN BIT(3) |
| 770 | #define RCC_MP_APB5LPENSETR_USART1LPEN BIT(4) |
| 771 | #define RCC_MP_APB5LPENSETR_RTCAPBLPEN BIT(8) |
| 772 | #define RCC_MP_APB5LPENSETR_TZC1LPEN BIT(11) |
| 773 | #define RCC_MP_APB5LPENSETR_TZC2LPEN BIT(12) |
| 774 | #define RCC_MP_APB5LPENSETR_TZPCLPEN BIT(13) |
| 775 | #define RCC_MP_APB5LPENSETR_IWDG1APBLPEN BIT(15) |
| 776 | #define RCC_MP_APB5LPENSETR_BSECLPEN BIT(16) |
| 777 | #define RCC_MP_APB5LPENSETR_STGENLPEN BIT(20) |
| 778 | #define RCC_MP_APB5LPENSETR_STGENSTPEN BIT(21) |
| 779 | |
| 780 | /* RCC_MP_APB5LPENCLRR register fields */ |
| 781 | #define RCC_MP_APB5LPENCLRR_SPI6LPEN BIT(0) |
| 782 | #define RCC_MP_APB5LPENCLRR_I2C4LPEN BIT(2) |
| 783 | #define RCC_MP_APB5LPENCLRR_I2C6LPEN BIT(3) |
| 784 | #define RCC_MP_APB5LPENCLRR_USART1LPEN BIT(4) |
| 785 | #define RCC_MP_APB5LPENCLRR_RTCAPBLPEN BIT(8) |
| 786 | #define RCC_MP_APB5LPENCLRR_TZC1LPEN BIT(11) |
| 787 | #define RCC_MP_APB5LPENCLRR_TZC2LPEN BIT(12) |
| 788 | #define RCC_MP_APB5LPENCLRR_TZPCLPEN BIT(13) |
| 789 | #define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN BIT(15) |
| 790 | #define RCC_MP_APB5LPENCLRR_BSECLPEN BIT(16) |
| 791 | #define RCC_MP_APB5LPENCLRR_STGENLPEN BIT(20) |
| 792 | #define RCC_MP_APB5LPENCLRR_STGENSTPEN BIT(21) |
| 793 | |
| 794 | /* RCC_MP_AHB5LPENSETR register fields */ |
| 795 | #define RCC_MP_AHB5LPENSETR_GPIOZLPEN BIT(0) |
| 796 | #define RCC_MP_AHB5LPENSETR_CRYP1LPEN BIT(4) |
| 797 | #define RCC_MP_AHB5LPENSETR_HASH1LPEN BIT(5) |
| 798 | #define RCC_MP_AHB5LPENSETR_RNG1LPEN BIT(6) |
| 799 | #define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN BIT(8) |
| 800 | |
| 801 | /* RCC_MP_AHB5LPENCLRR register fields */ |
| 802 | #define RCC_MP_AHB5LPENCLRR_GPIOZLPEN BIT(0) |
| 803 | #define RCC_MP_AHB5LPENCLRR_CRYP1LPEN BIT(4) |
| 804 | #define RCC_MP_AHB5LPENCLRR_HASH1LPEN BIT(5) |
| 805 | #define RCC_MP_AHB5LPENCLRR_RNG1LPEN BIT(6) |
| 806 | #define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN BIT(8) |
| 807 | |
| 808 | /* RCC_MP_AHB6LPENSETR register fields */ |
| 809 | #define RCC_MP_AHB6LPENSETR_MDMALPEN BIT(0) |
| 810 | #define RCC_MP_AHB6LPENSETR_GPULPEN BIT(5) |
| 811 | #define RCC_MP_AHB6LPENSETR_ETHCKLPEN BIT(7) |
| 812 | #define RCC_MP_AHB6LPENSETR_ETHTXLPEN BIT(8) |
| 813 | #define RCC_MP_AHB6LPENSETR_ETHRXLPEN BIT(9) |
| 814 | #define RCC_MP_AHB6LPENSETR_ETHMACLPEN BIT(10) |
| 815 | #define RCC_MP_AHB6LPENSETR_ETHSTPEN BIT(11) |
| 816 | #define RCC_MP_AHB6LPENSETR_FMCLPEN BIT(12) |
| 817 | #define RCC_MP_AHB6LPENSETR_QSPILPEN BIT(14) |
| 818 | #define RCC_MP_AHB6LPENSETR_SDMMC1LPEN BIT(16) |
| 819 | #define RCC_MP_AHB6LPENSETR_SDMMC2LPEN BIT(17) |
| 820 | #define RCC_MP_AHB6LPENSETR_CRC1LPEN BIT(20) |
| 821 | #define RCC_MP_AHB6LPENSETR_USBHLPEN BIT(24) |
| 822 | |
| 823 | /* RCC_MP_AHB6LPENCLRR register fields */ |
| 824 | #define RCC_MP_AHB6LPENCLRR_MDMALPEN BIT(0) |
| 825 | #define RCC_MP_AHB6LPENCLRR_GPULPEN BIT(5) |
| 826 | #define RCC_MP_AHB6LPENCLRR_ETHCKLPEN BIT(7) |
| 827 | #define RCC_MP_AHB6LPENCLRR_ETHTXLPEN BIT(8) |
| 828 | #define RCC_MP_AHB6LPENCLRR_ETHRXLPEN BIT(9) |
| 829 | #define RCC_MP_AHB6LPENCLRR_ETHMACLPEN BIT(10) |
| 830 | #define RCC_MP_AHB6LPENCLRR_ETHSTPEN BIT(11) |
| 831 | #define RCC_MP_AHB6LPENCLRR_FMCLPEN BIT(12) |
| 832 | #define RCC_MP_AHB6LPENCLRR_QSPILPEN BIT(14) |
| 833 | #define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN BIT(16) |
| 834 | #define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN BIT(17) |
| 835 | #define RCC_MP_AHB6LPENCLRR_CRC1LPEN BIT(20) |
| 836 | #define RCC_MP_AHB6LPENCLRR_USBHLPEN BIT(24) |
| 837 | |
| 838 | /* RCC_MP_TZAHB6LPENSETR register fields */ |
| 839 | #define RCC_MP_TZAHB6LPENSETR_MDMALPEN BIT(0) |
| 840 | |
| 841 | /* RCC_MP_TZAHB6LPENCLRR register fields */ |
| 842 | #define RCC_MP_TZAHB6LPENCLRR_MDMALPEN BIT(0) |
| 843 | |
| 844 | /* RCC_MC_APB4LPENSETR register fields */ |
| 845 | #define RCC_MC_APB4LPENSETR_LTDCLPEN BIT(0) |
| 846 | #define RCC_MC_APB4LPENSETR_DSILPEN BIT(4) |
| 847 | #define RCC_MC_APB4LPENSETR_DDRPERFMLPEN BIT(8) |
| 848 | #define RCC_MC_APB4LPENSETR_USBPHYLPEN BIT(16) |
| 849 | #define RCC_MC_APB4LPENSETR_STGENROLPEN BIT(20) |
| 850 | #define RCC_MC_APB4LPENSETR_STGENROSTPEN BIT(21) |
| 851 | |
| 852 | /* RCC_MC_APB4LPENCLRR register fields */ |
| 853 | #define RCC_MC_APB4LPENCLRR_LTDCLPEN BIT(0) |
| 854 | #define RCC_MC_APB4LPENCLRR_DSILPEN BIT(4) |
| 855 | #define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN BIT(8) |
| 856 | #define RCC_MC_APB4LPENCLRR_USBPHYLPEN BIT(16) |
| 857 | #define RCC_MC_APB4LPENCLRR_STGENROLPEN BIT(20) |
| 858 | #define RCC_MC_APB4LPENCLRR_STGENROSTPEN BIT(21) |
| 859 | |
| 860 | /* RCC_MC_APB5LPENSETR register fields */ |
| 861 | #define RCC_MC_APB5LPENSETR_SPI6LPEN BIT(0) |
| 862 | #define RCC_MC_APB5LPENSETR_I2C4LPEN BIT(2) |
| 863 | #define RCC_MC_APB5LPENSETR_I2C6LPEN BIT(3) |
| 864 | #define RCC_MC_APB5LPENSETR_USART1LPEN BIT(4) |
| 865 | #define RCC_MC_APB5LPENSETR_RTCAPBLPEN BIT(8) |
| 866 | #define RCC_MC_APB5LPENSETR_TZC1LPEN BIT(11) |
| 867 | #define RCC_MC_APB5LPENSETR_TZC2LPEN BIT(12) |
| 868 | #define RCC_MC_APB5LPENSETR_TZPCLPEN BIT(13) |
| 869 | #define RCC_MC_APB5LPENSETR_BSECLPEN BIT(16) |
| 870 | #define RCC_MC_APB5LPENSETR_STGENLPEN BIT(20) |
| 871 | #define RCC_MC_APB5LPENSETR_STGENSTPEN BIT(21) |
| 872 | |
| 873 | /* RCC_MC_APB5LPENCLRR register fields */ |
| 874 | #define RCC_MC_APB5LPENCLRR_SPI6LPEN BIT(0) |
| 875 | #define RCC_MC_APB5LPENCLRR_I2C4LPEN BIT(2) |
| 876 | #define RCC_MC_APB5LPENCLRR_I2C6LPEN BIT(3) |
| 877 | #define RCC_MC_APB5LPENCLRR_USART1LPEN BIT(4) |
| 878 | #define RCC_MC_APB5LPENCLRR_RTCAPBLPEN BIT(8) |
| 879 | #define RCC_MC_APB5LPENCLRR_TZC1LPEN BIT(11) |
| 880 | #define RCC_MC_APB5LPENCLRR_TZC2LPEN BIT(12) |
| 881 | #define RCC_MC_APB5LPENCLRR_TZPCLPEN BIT(13) |
| 882 | #define RCC_MC_APB5LPENCLRR_BSECLPEN BIT(16) |
| 883 | #define RCC_MC_APB5LPENCLRR_STGENLPEN BIT(20) |
| 884 | #define RCC_MC_APB5LPENCLRR_STGENSTPEN BIT(21) |
| 885 | |
| 886 | /* RCC_MC_AHB5LPENSETR register fields */ |
| 887 | #define RCC_MC_AHB5LPENSETR_GPIOZLPEN BIT(0) |
| 888 | #define RCC_MC_AHB5LPENSETR_CRYP1LPEN BIT(4) |
| 889 | #define RCC_MC_AHB5LPENSETR_HASH1LPEN BIT(5) |
| 890 | #define RCC_MC_AHB5LPENSETR_RNG1LPEN BIT(6) |
| 891 | #define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN BIT(8) |
| 892 | |
| 893 | /* RCC_MC_AHB5LPENCLRR register fields */ |
| 894 | #define RCC_MC_AHB5LPENCLRR_GPIOZLPEN BIT(0) |
| 895 | #define RCC_MC_AHB5LPENCLRR_CRYP1LPEN BIT(4) |
| 896 | #define RCC_MC_AHB5LPENCLRR_HASH1LPEN BIT(5) |
| 897 | #define RCC_MC_AHB5LPENCLRR_RNG1LPEN BIT(6) |
| 898 | #define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN BIT(8) |
| 899 | |
| 900 | /* RCC_MC_AHB6LPENSETR register fields */ |
| 901 | #define RCC_MC_AHB6LPENSETR_MDMALPEN BIT(0) |
| 902 | #define RCC_MC_AHB6LPENSETR_GPULPEN BIT(5) |
| 903 | #define RCC_MC_AHB6LPENSETR_ETHCKLPEN BIT(7) |
| 904 | #define RCC_MC_AHB6LPENSETR_ETHTXLPEN BIT(8) |
| 905 | #define RCC_MC_AHB6LPENSETR_ETHRXLPEN BIT(9) |
| 906 | #define RCC_MC_AHB6LPENSETR_ETHMACLPEN BIT(10) |
| 907 | #define RCC_MC_AHB6LPENSETR_ETHSTPEN BIT(11) |
| 908 | #define RCC_MC_AHB6LPENSETR_FMCLPEN BIT(12) |
| 909 | #define RCC_MC_AHB6LPENSETR_QSPILPEN BIT(14) |
| 910 | #define RCC_MC_AHB6LPENSETR_SDMMC1LPEN BIT(16) |
| 911 | #define RCC_MC_AHB6LPENSETR_SDMMC2LPEN BIT(17) |
| 912 | #define RCC_MC_AHB6LPENSETR_CRC1LPEN BIT(20) |
| 913 | #define RCC_MC_AHB6LPENSETR_USBHLPEN BIT(24) |
| 914 | |
| 915 | /* RCC_MC_AHB6LPENCLRR register fields */ |
| 916 | #define RCC_MC_AHB6LPENCLRR_MDMALPEN BIT(0) |
| 917 | #define RCC_MC_AHB6LPENCLRR_GPULPEN BIT(5) |
| 918 | #define RCC_MC_AHB6LPENCLRR_ETHCKLPEN BIT(7) |
| 919 | #define RCC_MC_AHB6LPENCLRR_ETHTXLPEN BIT(8) |
| 920 | #define RCC_MC_AHB6LPENCLRR_ETHRXLPEN BIT(9) |
| 921 | #define RCC_MC_AHB6LPENCLRR_ETHMACLPEN BIT(10) |
| 922 | #define RCC_MC_AHB6LPENCLRR_ETHSTPEN BIT(11) |
| 923 | #define RCC_MC_AHB6LPENCLRR_FMCLPEN BIT(12) |
| 924 | #define RCC_MC_AHB6LPENCLRR_QSPILPEN BIT(14) |
| 925 | #define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN BIT(16) |
| 926 | #define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN BIT(17) |
| 927 | #define RCC_MC_AHB6LPENCLRR_CRC1LPEN BIT(20) |
| 928 | #define RCC_MC_AHB6LPENCLRR_USBHLPEN BIT(24) |
| 929 | |
| 930 | /* RCC_BR_RSTSCLRR register fields */ |
| 931 | #define RCC_BR_RSTSCLRR_PORRSTF BIT(0) |
| 932 | #define RCC_BR_RSTSCLRR_BORRSTF BIT(1) |
| 933 | #define RCC_BR_RSTSCLRR_PADRSTF BIT(2) |
| 934 | #define RCC_BR_RSTSCLRR_HCSSRSTF BIT(3) |
| 935 | #define RCC_BR_RSTSCLRR_VCORERSTF BIT(4) |
| 936 | #define RCC_BR_RSTSCLRR_MPSYSRSTF BIT(6) |
| 937 | #define RCC_BR_RSTSCLRR_MCSYSRSTF BIT(7) |
| 938 | #define RCC_BR_RSTSCLRR_IWDG1RSTF BIT(8) |
| 939 | #define RCC_BR_RSTSCLRR_IWDG2RSTF BIT(9) |
| 940 | #define RCC_BR_RSTSCLRR_MPUP0RSTF BIT(13) |
| 941 | #define RCC_BR_RSTSCLRR_MPUP1RSTF BIT(14) |
| 942 | |
| 943 | /* RCC_MP_GRSTCSETR register fields */ |
| 944 | #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) |
| 945 | #define RCC_MP_GRSTCSETR_MCURST BIT(1) |
| 946 | #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) |
| 947 | #define RCC_MP_GRSTCSETR_MPUP1RST BIT(5) |
| 948 | |
| 949 | /* RCC_MP_RSTSCLRR register fields */ |
| 950 | #define RCC_MP_RSTSCLRR_PORRSTF BIT(0) |
| 951 | #define RCC_MP_RSTSCLRR_BORRSTF BIT(1) |
| 952 | #define RCC_MP_RSTSCLRR_PADRSTF BIT(2) |
| 953 | #define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3) |
| 954 | #define RCC_MP_RSTSCLRR_VCORERSTF BIT(4) |
| 955 | #define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6) |
| 956 | #define RCC_MP_RSTSCLRR_MCSYSRSTF BIT(7) |
| 957 | #define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8) |
| 958 | #define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9) |
| 959 | #define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11) |
| 960 | #define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12) |
| 961 | #define RCC_MP_RSTSCLRR_MPUP0RSTF BIT(13) |
| 962 | #define RCC_MP_RSTSCLRR_MPUP1RSTF BIT(14) |
| 963 | #define RCC_MP_RSTSCLRR_SPARE BIT(15) |
| 964 | |
| 965 | /* RCC_MP_IWDGFZSETR register fields */ |
| 966 | #define RCC_MP_IWDGFZSETR_FZ_IWDG1 BIT(0) |
| 967 | #define RCC_MP_IWDGFZSETR_FZ_IWDG2 BIT(1) |
| 968 | |
| 969 | /* RCC_MP_IWDGFZCLRR register fields */ |
| 970 | #define RCC_MP_IWDGFZCLRR_FZ_IWDG1 BIT(0) |
| 971 | #define RCC_MP_IWDGFZCLRR_FZ_IWDG2 BIT(1) |
| 972 | |
| 973 | /* RCC_MP_CIER register fields */ |
| 974 | #define RCC_MP_CIER_LSIRDYIE BIT(0) |
| 975 | #define RCC_MP_CIER_LSERDYIE BIT(1) |
| 976 | #define RCC_MP_CIER_HSIRDYIE BIT(2) |
| 977 | #define RCC_MP_CIER_HSERDYIE BIT(3) |
| 978 | #define RCC_MP_CIER_CSIRDYIE BIT(4) |
| 979 | #define RCC_MP_CIER_PLL1DYIE BIT(8) |
| 980 | #define RCC_MP_CIER_PLL2DYIE BIT(9) |
| 981 | #define RCC_MP_CIER_PLL3DYIE BIT(10) |
| 982 | #define RCC_MP_CIER_PLL4DYIE BIT(11) |
| 983 | #define RCC_MP_CIER_LSECSSIE BIT(16) |
| 984 | #define RCC_MP_CIER_WKUPIE BIT(20) |
| 985 | |
| 986 | /* RCC_MP_CIFR register fields */ |
| 987 | #define RCC_MP_CIFR_MASK U(0x110F1F) |
| 988 | #define RCC_MP_CIFR_LSIRDYF BIT(0) |
| 989 | #define RCC_MP_CIFR_LSERDYF BIT(1) |
| 990 | #define RCC_MP_CIFR_HSIRDYF BIT(2) |
| 991 | #define RCC_MP_CIFR_HSERDYF BIT(3) |
| 992 | #define RCC_MP_CIFR_CSIRDYF BIT(4) |
| 993 | #define RCC_MP_CIFR_PLL1DYF BIT(8) |
| 994 | #define RCC_MP_CIFR_PLL2DYF BIT(9) |
| 995 | #define RCC_MP_CIFR_PLL3DYF BIT(10) |
| 996 | #define RCC_MP_CIFR_PLL4DYF BIT(11) |
| 997 | #define RCC_MP_CIFR_LSECSSF BIT(16) |
| 998 | #define RCC_MP_CIFR_WKUPF BIT(20) |
| 999 | |
| 1000 | /* RCC_PWRLPDLYCR register fields */ |
| 1001 | #define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0) |
| 1002 | #define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0 |
| 1003 | #define RCC_PWRLPDLYCR_MCTMPSKP BIT(24) |
| 1004 | |
| 1005 | /* RCC_MP_RSTSSETR register fields */ |
| 1006 | #define RCC_MP_RSTSSETR_PORRSTF BIT(0) |
| 1007 | #define RCC_MP_RSTSSETR_BORRSTF BIT(1) |
| 1008 | #define RCC_MP_RSTSSETR_PADRSTF BIT(2) |
| 1009 | #define RCC_MP_RSTSSETR_HCSSRSTF BIT(3) |
| 1010 | #define RCC_MP_RSTSSETR_VCORERSTF BIT(4) |
| 1011 | #define RCC_MP_RSTSSETR_MPSYSRSTF BIT(6) |
| 1012 | #define RCC_MP_RSTSSETR_MCSYSRSTF BIT(7) |
| 1013 | #define RCC_MP_RSTSSETR_IWDG1RSTF BIT(8) |
| 1014 | #define RCC_MP_RSTSSETR_IWDG2RSTF BIT(9) |
| 1015 | #define RCC_MP_RSTSSETR_STDBYRSTF BIT(11) |
| 1016 | #define RCC_MP_RSTSSETR_CSTDBYRSTF BIT(12) |
| 1017 | #define RCC_MP_RSTSSETR_MPUP0RSTF BIT(13) |
| 1018 | #define RCC_MP_RSTSSETR_MPUP1RSTF BIT(14) |
| 1019 | #define RCC_MP_RSTSSETR_SPARE BIT(15) |
| 1020 | |
| 1021 | /* RCC_MCO1CFGR register fields */ |
| 1022 | #define RCC_MCO1CFGR_MCO1SEL_MASK GENMASK(2, 0) |
| 1023 | #define RCC_MCO1CFGR_MCO1SEL_SHIFT 0 |
| 1024 | #define RCC_MCO1CFGR_MCO1DIV_MASK GENMASK(7, 4) |
| 1025 | #define RCC_MCO1CFGR_MCO1DIV_SHIFT 4 |
| 1026 | #define RCC_MCO1CFGR_MCO1ON BIT(12) |
| 1027 | |
| 1028 | /* RCC_MCO2CFGR register fields */ |
| 1029 | #define RCC_MCO2CFGR_MCO2SEL_MASK GENMASK(2, 0) |
| 1030 | #define RCC_MCO2CFGR_MCO2SEL_SHIFT 0 |
| 1031 | #define RCC_MCO2CFGR_MCO2DIV_MASK GENMASK(7, 4) |
| 1032 | #define RCC_MCO2CFGR_MCO2DIV_SHIFT 4 |
| 1033 | #define RCC_MCO2CFGR_MCO2ON BIT(12) |
| 1034 | |
| 1035 | /* RCC_OCRDYR register fields */ |
| 1036 | #define RCC_OCRDYR_HSIRDY BIT(0) |
| 1037 | #define RCC_OCRDYR_HSIDIVRDY BIT(2) |
| 1038 | #define RCC_OCRDYR_CSIRDY BIT(4) |
| 1039 | #define RCC_OCRDYR_HSERDY BIT(8) |
| 1040 | #define RCC_OCRDYR_MPUCKRDY BIT(23) |
| 1041 | #define RCC_OCRDYR_AXICKRDY BIT(24) |
| 1042 | #define RCC_OCRDYR_CKREST BIT(25) |
| 1043 | |
| 1044 | /* RCC_DBGCFGR register fields */ |
| 1045 | #define RCC_DBGCFGR_TRACEDIV_MASK GENMASK(2, 0) |
| 1046 | #define RCC_DBGCFGR_TRACEDIV_SHIFT 0 |
| 1047 | #define RCC_DBGCFGR_DBGCKEN BIT(8) |
| 1048 | #define RCC_DBGCFGR_TRACECKEN BIT(9) |
| 1049 | #define RCC_DBGCFGR_DBGRST BIT(12) |
| 1050 | |
| 1051 | /* RCC_RCK3SELR register fields */ |
| 1052 | #define RCC_RCK3SELR_PLL3SRC_MASK GENMASK(1, 0) |
| 1053 | #define RCC_RCK3SELR_PLL3SRC_SHIFT 0 |
| 1054 | #define RCC_RCK3SELR_PLL3SRCRDY BIT(31) |
| 1055 | |
| 1056 | /* RCC_RCK4SELR register fields */ |
| 1057 | #define RCC_RCK4SELR_PLL4SRC_MASK GENMASK(1, 0) |
| 1058 | #define RCC_RCK4SELR_PLL4SRC_SHIFT 0 |
| 1059 | #define RCC_RCK4SELR_PLL4SRCRDY BIT(31) |
| 1060 | |
| 1061 | /* RCC_TIMG1PRER register fields */ |
| 1062 | #define RCC_TIMG1PRER_TIMG1PRE BIT(0) |
| 1063 | #define RCC_TIMG1PRER_TIMG1PRERDY BIT(31) |
| 1064 | |
| 1065 | /* RCC_TIMG2PRER register fields */ |
| 1066 | #define RCC_TIMG2PRER_TIMG2PRE BIT(0) |
| 1067 | #define RCC_TIMG2PRER_TIMG2PRERDY BIT(31) |
| 1068 | |
| 1069 | /* RCC_MCUDIVR register fields */ |
| 1070 | #define RCC_MCUDIVR_MCUDIV_MASK GENMASK(3, 0) |
| 1071 | #define RCC_MCUDIVR_MCUDIV_SHIFT 0 |
| 1072 | #define RCC_MCUDIVR_MCUDIVRDY BIT(31) |
| 1073 | |
| 1074 | /* RCC_APB1DIVR register fields */ |
| 1075 | #define RCC_APB1DIVR_APB1DIV_MASK GENMASK(2, 0) |
| 1076 | #define RCC_APB1DIVR_APB1DIV_SHIFT 0 |
| 1077 | #define RCC_APB1DIVR_APB1DIVRDY BIT(31) |
| 1078 | |
| 1079 | /* RCC_APB2DIVR register fields */ |
| 1080 | #define RCC_APB2DIVR_APB2DIV_MASK GENMASK(2, 0) |
| 1081 | #define RCC_APB2DIVR_APB2DIV_SHIFT 0 |
| 1082 | #define RCC_APB2DIVR_APB2DIVRDY BIT(31) |
| 1083 | |
| 1084 | /* RCC_APB3DIVR register fields */ |
| 1085 | #define RCC_APB3DIVR_APB3DIV_MASK GENMASK(2, 0) |
| 1086 | #define RCC_APB3DIVR_APB3DIV_SHIFT 0 |
| 1087 | #define RCC_APB3DIVR_APB3DIVRDY BIT(31) |
| 1088 | |
| 1089 | /* RCC_PLL3CR register fields */ |
| 1090 | #define RCC_PLL3CR_PLLON BIT(0) |
| 1091 | #define RCC_PLL3CR_PLL3RDY BIT(1) |
| 1092 | #define RCC_PLL3CR_SSCG_CTRL BIT(2) |
| 1093 | #define RCC_PLL3CR_DIVPEN BIT(4) |
| 1094 | #define RCC_PLL3CR_DIVQEN BIT(5) |
| 1095 | #define RCC_PLL3CR_DIVREN BIT(6) |
| 1096 | |
| 1097 | /* RCC_PLL3CFGR1 register fields */ |
| 1098 | #define RCC_PLL3CFGR1_DIVN_MASK GENMASK(8, 0) |
| 1099 | #define RCC_PLL3CFGR1_DIVN_SHIFT 0 |
| 1100 | #define RCC_PLL3CFGR1_DIVM3_MASK GENMASK(21, 16) |
| 1101 | #define RCC_PLL3CFGR1_DIVM3_SHIFT 16 |
| 1102 | #define RCC_PLL3CFGR1_IFRGE_MASK GENMASK(25, 24) |
| 1103 | #define RCC_PLL3CFGR1_IFRGE_SHIFT 24 |
| 1104 | |
| 1105 | /* RCC_PLL3CFGR2 register fields */ |
| 1106 | #define RCC_PLL3CFGR2_DIVP_MASK GENMASK(6, 0) |
| 1107 | #define RCC_PLL3CFGR2_DIVP_SHIFT 0 |
| 1108 | #define RCC_PLL3CFGR2_DIVQ_MASK GENMASK(14, 8) |
| 1109 | #define RCC_PLL3CFGR2_DIVQ_SHIFT 8 |
| 1110 | #define RCC_PLL3CFGR2_DIVR_MASK GENMASK(22, 16) |
| 1111 | #define RCC_PLL3CFGR2_DIVR_SHIFT 16 |
| 1112 | |
| 1113 | /* RCC_PLL3FRACR register fields */ |
| 1114 | #define RCC_PLL3FRACR_FRACV_MASK GENMASK(15, 3) |
| 1115 | #define RCC_PLL3FRACR_FRACV_SHIFT 3 |
| 1116 | #define RCC_PLL3FRACR_FRACLE BIT(16) |
| 1117 | |
| 1118 | /* RCC_PLL3CSGR register fields */ |
| 1119 | #define RCC_PLL3CSGR_MOD_PER_MASK GENMASK(12, 0) |
| 1120 | #define RCC_PLL3CSGR_MOD_PER_SHIFT 0 |
| 1121 | #define RCC_PLL3CSGR_TPDFN_DIS BIT(13) |
| 1122 | #define RCC_PLL3CSGR_RPDFN_DIS BIT(14) |
| 1123 | #define RCC_PLL3CSGR_SSCG_MODE BIT(15) |
| 1124 | #define RCC_PLL3CSGR_INC_STEP_MASK GENMASK(30, 16) |
| 1125 | #define RCC_PLL3CSGR_INC_STEP_SHIFT 16 |
| 1126 | |
| 1127 | /* RCC_PLL4CR register fields */ |
| 1128 | #define RCC_PLL4CR_PLLON BIT(0) |
| 1129 | #define RCC_PLL4CR_PLL4RDY BIT(1) |
| 1130 | #define RCC_PLL4CR_SSCG_CTRL BIT(2) |
| 1131 | #define RCC_PLL4CR_DIVPEN BIT(4) |
| 1132 | #define RCC_PLL4CR_DIVQEN BIT(5) |
| 1133 | #define RCC_PLL4CR_DIVREN BIT(6) |
| 1134 | |
| 1135 | /* RCC_PLL4CFGR1 register fields */ |
| 1136 | #define RCC_PLL4CFGR1_DIVN_MASK GENMASK(8, 0) |
| 1137 | #define RCC_PLL4CFGR1_DIVN_SHIFT 0 |
| 1138 | #define RCC_PLL4CFGR1_DIVM4_MASK GENMASK(21, 16) |
| 1139 | #define RCC_PLL4CFGR1_DIVM4_SHIFT 16 |
| 1140 | #define RCC_PLL4CFGR1_IFRGE_MASK GENMASK(25, 24) |
| 1141 | #define RCC_PLL4CFGR1_IFRGE_SHIFT 24 |
| 1142 | |
| 1143 | /* RCC_PLL4CFGR2 register fields */ |
| 1144 | #define RCC_PLL4CFGR2_DIVP_MASK GENMASK(6, 0) |
| 1145 | #define RCC_PLL4CFGR2_DIVP_SHIFT 0 |
| 1146 | #define RCC_PLL4CFGR2_DIVQ_MASK GENMASK(14, 8) |
| 1147 | #define RCC_PLL4CFGR2_DIVQ_SHIFT 8 |
| 1148 | #define RCC_PLL4CFGR2_DIVR_MASK GENMASK(22, 16) |
| 1149 | #define RCC_PLL4CFGR2_DIVR_SHIFT 16 |
| 1150 | |
| 1151 | /* RCC_PLL4FRACR register fields */ |
| 1152 | #define RCC_PLL4FRACR_FRACV_MASK GENMASK(15, 3) |
| 1153 | #define RCC_PLL4FRACR_FRACV_SHIFT 3 |
| 1154 | #define RCC_PLL4FRACR_FRACLE BIT(16) |
| 1155 | |
| 1156 | /* RCC_PLL4CSGR register fields */ |
| 1157 | #define RCC_PLL4CSGR_MOD_PER_MASK GENMASK(12, 0) |
| 1158 | #define RCC_PLL4CSGR_MOD_PER_SHIFT 0 |
| 1159 | #define RCC_PLL4CSGR_TPDFN_DIS BIT(13) |
| 1160 | #define RCC_PLL4CSGR_RPDFN_DIS BIT(14) |
| 1161 | #define RCC_PLL4CSGR_SSCG_MODE BIT(15) |
| 1162 | #define RCC_PLL4CSGR_INC_STEP_MASK GENMASK(30, 16) |
| 1163 | #define RCC_PLL4CSGR_INC_STEP_SHIFT 16 |
| 1164 | |
| 1165 | /* RCC_I2C12CKSELR register fields */ |
| 1166 | #define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0) |
| 1167 | #define RCC_I2C12CKSELR_I2C12SRC_SHIFT 0 |
| 1168 | |
| 1169 | /* RCC_I2C35CKSELR register fields */ |
| 1170 | #define RCC_I2C35CKSELR_I2C35SRC_MASK GENMASK(2, 0) |
| 1171 | #define RCC_I2C35CKSELR_I2C35SRC_SHIFT 0 |
| 1172 | |
| 1173 | /* RCC_SAI1CKSELR register fields */ |
| 1174 | #define RCC_SAI1CKSELR_SAI1SRC_MASK GENMASK(2, 0) |
| 1175 | #define RCC_SAI1CKSELR_SAI1SRC_SHIFT 0 |
| 1176 | |
| 1177 | /* RCC_SAI2CKSELR register fields */ |
| 1178 | #define RCC_SAI2CKSELR_SAI2SRC_MASK GENMASK(2, 0) |
| 1179 | #define RCC_SAI2CKSELR_SAI2SRC_SHIFT 0 |
| 1180 | |
| 1181 | /* RCC_SAI3CKSELR register fields */ |
| 1182 | #define RCC_SAI3CKSELR_SAI3SRC_MASK GENMASK(2, 0) |
| 1183 | #define RCC_SAI3CKSELR_SAI3SRC_SHIFT 0 |
| 1184 | |
| 1185 | /* RCC_SAI4CKSELR register fields */ |
| 1186 | #define RCC_SAI4CKSELR_SAI4SRC_MASK GENMASK(2, 0) |
| 1187 | #define RCC_SAI4CKSELR_SAI4SRC_SHIFT 0 |
| 1188 | |
| 1189 | /* RCC_SPI2S1CKSELR register fields */ |
| 1190 | #define RCC_SPI2S1CKSELR_SPI1SRC_MASK GENMASK(2, 0) |
| 1191 | #define RCC_SPI2S1CKSELR_SPI1SRC_SHIFT 0 |
| 1192 | |
| 1193 | /* RCC_SPI2S23CKSELR register fields */ |
| 1194 | #define RCC_SPI2S23CKSELR_SPI23SRC_MASK GENMASK(2, 0) |
| 1195 | #define RCC_SPI2S23CKSELR_SPI23SRC_SHIFT 0 |
| 1196 | |
| 1197 | /* RCC_SPI45CKSELR register fields */ |
| 1198 | #define RCC_SPI45CKSELR_SPI45SRC_MASK GENMASK(2, 0) |
| 1199 | #define RCC_SPI45CKSELR_SPI45SRC_SHIFT 0 |
| 1200 | |
| 1201 | /* RCC_UART6CKSELR register fields */ |
| 1202 | #define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0) |
| 1203 | #define RCC_UART6CKSELR_UART6SRC_SHIFT 0 |
| 1204 | |
| 1205 | /* RCC_UART24CKSELR register fields */ |
| 1206 | #define RCC_UART24CKSELR_HSI 0x00000002 |
| 1207 | #define RCC_UART24CKSELR_UART24SRC_MASK GENMASK(2, 0) |
| 1208 | #define RCC_UART24CKSELR_UART24SRC_SHIFT 0 |
| 1209 | |
| 1210 | /* RCC_UART35CKSELR register fields */ |
| 1211 | #define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0) |
| 1212 | #define RCC_UART35CKSELR_UART35SRC_SHIFT 0 |
| 1213 | |
| 1214 | /* RCC_UART78CKSELR register fields */ |
| 1215 | #define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0) |
| 1216 | #define RCC_UART78CKSELR_UART78SRC_SHIFT 0 |
| 1217 | |
| 1218 | /* RCC_SDMMC12CKSELR register fields */ |
| 1219 | #define RCC_SDMMC12CKSELR_SDMMC12SRC_MASK GENMASK(2, 0) |
| 1220 | #define RCC_SDMMC12CKSELR_SDMMC12SRC_SHIFT 0 |
| 1221 | |
| 1222 | /* RCC_SDMMC3CKSELR register fields */ |
| 1223 | #define RCC_SDMMC3CKSELR_SDMMC3SRC_MASK GENMASK(2, 0) |
| 1224 | #define RCC_SDMMC3CKSELR_SDMMC3SRC_SHIFT 0 |
| 1225 | |
| 1226 | /* RCC_ETHCKSELR register fields */ |
| 1227 | #define RCC_ETHCKSELR_ETHSRC_MASK GENMASK(1, 0) |
| 1228 | #define RCC_ETHCKSELR_ETHSRC_SHIFT 0 |
| 1229 | #define RCC_ETHCKSELR_ETHPTPDIV_MASK GENMASK(7, 4) |
| 1230 | #define RCC_ETHCKSELR_ETHPTPDIV_SHIFT 4 |
| 1231 | |
| 1232 | /* RCC_QSPICKSELR register fields */ |
| 1233 | #define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0) |
| 1234 | #define RCC_QSPICKSELR_QSPISRC_SHIFT 0 |
| 1235 | |
| 1236 | /* RCC_FMCCKSELR register fields */ |
| 1237 | #define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0) |
| 1238 | #define RCC_FMCCKSELR_FMCSRC_SHIFT 0 |
| 1239 | |
| 1240 | /* RCC_FDCANCKSELR register fields */ |
| 1241 | #define RCC_FDCANCKSELR_FDCANSRC_MASK GENMASK(1, 0) |
| 1242 | #define RCC_FDCANCKSELR_FDCANSRC_SHIFT 0 |
| 1243 | |
| 1244 | /* RCC_SPDIFCKSELR register fields */ |
| 1245 | #define RCC_SPDIFCKSELR_SPDIFSRC_MASK GENMASK(1, 0) |
| 1246 | #define RCC_SPDIFCKSELR_SPDIFSRC_SHIFT 0 |
| 1247 | |
| 1248 | /* RCC_CECCKSELR register fields */ |
| 1249 | #define RCC_CECCKSELR_CECSRC_MASK GENMASK(1, 0) |
| 1250 | #define RCC_CECCKSELR_CECSRC_SHIFT 0 |
| 1251 | |
| 1252 | /* RCC_USBCKSELR register fields */ |
| 1253 | #define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0) |
| 1254 | #define RCC_USBCKSELR_USBPHYSRC_SHIFT 0 |
| 1255 | #define RCC_USBCKSELR_USBOSRC BIT(4) |
| 1256 | #define RCC_USBCKSELR_USBOSRC_MASK BIT(4) |
| 1257 | #define RCC_USBCKSELR_USBOSRC_SHIFT 4 |
| 1258 | |
| 1259 | /* RCC_RNG2CKSELR register fields */ |
| 1260 | #define RCC_RNG2CKSELR_RNG2SRC_MASK GENMASK(1, 0) |
| 1261 | #define RCC_RNG2CKSELR_RNG2SRC_SHIFT 0 |
| 1262 | |
| 1263 | /* RCC_DSICKSELR register fields */ |
| 1264 | #define RCC_DSICKSELR_DSISRC BIT(0) |
| 1265 | |
| 1266 | /* RCC_ADCCKSELR register fields */ |
| 1267 | #define RCC_ADCCKSELR_ADCSRC_MASK GENMASK(1, 0) |
| 1268 | #define RCC_ADCCKSELR_ADCSRC_SHIFT 0 |
| 1269 | |
| 1270 | /* RCC_LPTIM45CKSELR register fields */ |
| 1271 | #define RCC_LPTIM45CKSELR_LPTIM45SRC_MASK GENMASK(2, 0) |
| 1272 | #define RCC_LPTIM45CKSELR_LPTIM45SRC_SHIFT 0 |
| 1273 | |
| 1274 | /* RCC_LPTIM23CKSELR register fields */ |
| 1275 | #define RCC_LPTIM23CKSELR_LPTIM23SRC_MASK GENMASK(2, 0) |
| 1276 | #define RCC_LPTIM23CKSELR_LPTIM23SRC_SHIFT 0 |
| 1277 | |
| 1278 | /* RCC_LPTIM1CKSELR register fields */ |
| 1279 | #define RCC_LPTIM1CKSELR_LPTIM1SRC_MASK GENMASK(2, 0) |
| 1280 | #define RCC_LPTIM1CKSELR_LPTIM1SRC_SHIFT 0 |
| 1281 | |
| 1282 | /* RCC_APB1RSTSETR register fields */ |
| 1283 | #define RCC_APB1RSTSETR_TIM2RST BIT(0) |
| 1284 | #define RCC_APB1RSTSETR_TIM3RST BIT(1) |
| 1285 | #define RCC_APB1RSTSETR_TIM4RST BIT(2) |
| 1286 | #define RCC_APB1RSTSETR_TIM5RST BIT(3) |
| 1287 | #define RCC_APB1RSTSETR_TIM6RST BIT(4) |
| 1288 | #define RCC_APB1RSTSETR_TIM7RST BIT(5) |
| 1289 | #define RCC_APB1RSTSETR_TIM12RST BIT(6) |
| 1290 | #define RCC_APB1RSTSETR_TIM13RST BIT(7) |
| 1291 | #define RCC_APB1RSTSETR_TIM14RST BIT(8) |
| 1292 | #define RCC_APB1RSTSETR_LPTIM1RST BIT(9) |
| 1293 | #define RCC_APB1RSTSETR_SPI2RST BIT(11) |
| 1294 | #define RCC_APB1RSTSETR_SPI3RST BIT(12) |
| 1295 | #define RCC_APB1RSTSETR_USART2RST BIT(14) |
| 1296 | #define RCC_APB1RSTSETR_USART3RST BIT(15) |
| 1297 | #define RCC_APB1RSTSETR_UART4RST BIT(16) |
| 1298 | #define RCC_APB1RSTSETR_UART5RST BIT(17) |
| 1299 | #define RCC_APB1RSTSETR_UART7RST BIT(18) |
| 1300 | #define RCC_APB1RSTSETR_UART8RST BIT(19) |
| 1301 | #define RCC_APB1RSTSETR_I2C1RST BIT(21) |
| 1302 | #define RCC_APB1RSTSETR_I2C2RST BIT(22) |
| 1303 | #define RCC_APB1RSTSETR_I2C3RST BIT(23) |
| 1304 | #define RCC_APB1RSTSETR_I2C5RST BIT(24) |
| 1305 | #define RCC_APB1RSTSETR_SPDIFRST BIT(26) |
| 1306 | #define RCC_APB1RSTSETR_CECRST BIT(27) |
| 1307 | #define RCC_APB1RSTSETR_DAC12RST BIT(29) |
| 1308 | #define RCC_APB1RSTSETR_MDIOSRST BIT(31) |
| 1309 | |
| 1310 | /* RCC_APB1RSTCLRR register fields */ |
| 1311 | #define RCC_APB1RSTCLRR_TIM2RST BIT(0) |
| 1312 | #define RCC_APB1RSTCLRR_TIM3RST BIT(1) |
| 1313 | #define RCC_APB1RSTCLRR_TIM4RST BIT(2) |
| 1314 | #define RCC_APB1RSTCLRR_TIM5RST BIT(3) |
| 1315 | #define RCC_APB1RSTCLRR_TIM6RST BIT(4) |
| 1316 | #define RCC_APB1RSTCLRR_TIM7RST BIT(5) |
| 1317 | #define RCC_APB1RSTCLRR_TIM12RST BIT(6) |
| 1318 | #define RCC_APB1RSTCLRR_TIM13RST BIT(7) |
| 1319 | #define RCC_APB1RSTCLRR_TIM14RST BIT(8) |
| 1320 | #define RCC_APB1RSTCLRR_LPTIM1RST BIT(9) |
| 1321 | #define RCC_APB1RSTCLRR_SPI2RST BIT(11) |
| 1322 | #define RCC_APB1RSTCLRR_SPI3RST BIT(12) |
| 1323 | #define RCC_APB1RSTCLRR_USART2RST BIT(14) |
| 1324 | #define RCC_APB1RSTCLRR_USART3RST BIT(15) |
| 1325 | #define RCC_APB1RSTCLRR_UART4RST BIT(16) |
| 1326 | #define RCC_APB1RSTCLRR_UART5RST BIT(17) |
| 1327 | #define RCC_APB1RSTCLRR_UART7RST BIT(18) |
| 1328 | #define RCC_APB1RSTCLRR_UART8RST BIT(19) |
| 1329 | #define RCC_APB1RSTCLRR_I2C1RST BIT(21) |
| 1330 | #define RCC_APB1RSTCLRR_I2C2RST BIT(22) |
| 1331 | #define RCC_APB1RSTCLRR_I2C3RST BIT(23) |
| 1332 | #define RCC_APB1RSTCLRR_I2C5RST BIT(24) |
| 1333 | #define RCC_APB1RSTCLRR_SPDIFRST BIT(26) |
| 1334 | #define RCC_APB1RSTCLRR_CECRST BIT(27) |
| 1335 | #define RCC_APB1RSTCLRR_DAC12RST BIT(29) |
| 1336 | #define RCC_APB1RSTCLRR_MDIOSRST BIT(31) |
| 1337 | |
| 1338 | /* RCC_APB2RSTSETR register fields */ |
| 1339 | #define RCC_APB2RSTSETR_TIM1RST BIT(0) |
| 1340 | #define RCC_APB2RSTSETR_TIM8RST BIT(1) |
| 1341 | #define RCC_APB2RSTSETR_TIM15RST BIT(2) |
| 1342 | #define RCC_APB2RSTSETR_TIM16RST BIT(3) |
| 1343 | #define RCC_APB2RSTSETR_TIM17RST BIT(4) |
| 1344 | #define RCC_APB2RSTSETR_SPI1RST BIT(8) |
| 1345 | #define RCC_APB2RSTSETR_SPI4RST BIT(9) |
| 1346 | #define RCC_APB2RSTSETR_SPI5RST BIT(10) |
| 1347 | #define RCC_APB2RSTSETR_USART6RST BIT(13) |
| 1348 | #define RCC_APB2RSTSETR_SAI1RST BIT(16) |
| 1349 | #define RCC_APB2RSTSETR_SAI2RST BIT(17) |
| 1350 | #define RCC_APB2RSTSETR_SAI3RST BIT(18) |
| 1351 | #define RCC_APB2RSTSETR_DFSDMRST BIT(20) |
| 1352 | #define RCC_APB2RSTSETR_FDCANRST BIT(24) |
| 1353 | |
| 1354 | /* RCC_APB2RSTCLRR register fields */ |
| 1355 | #define RCC_APB2RSTCLRR_TIM1RST BIT(0) |
| 1356 | #define RCC_APB2RSTCLRR_TIM8RST BIT(1) |
| 1357 | #define RCC_APB2RSTCLRR_TIM15RST BIT(2) |
| 1358 | #define RCC_APB2RSTCLRR_TIM16RST BIT(3) |
| 1359 | #define RCC_APB2RSTCLRR_TIM17RST BIT(4) |
| 1360 | #define RCC_APB2RSTCLRR_SPI1RST BIT(8) |
| 1361 | #define RCC_APB2RSTCLRR_SPI4RST BIT(9) |
| 1362 | #define RCC_APB2RSTCLRR_SPI5RST BIT(10) |
| 1363 | #define RCC_APB2RSTCLRR_USART6RST BIT(13) |
| 1364 | #define RCC_APB2RSTCLRR_SAI1RST BIT(16) |
| 1365 | #define RCC_APB2RSTCLRR_SAI2RST BIT(17) |
| 1366 | #define RCC_APB2RSTCLRR_SAI3RST BIT(18) |
| 1367 | #define RCC_APB2RSTCLRR_DFSDMRST BIT(20) |
| 1368 | #define RCC_APB2RSTCLRR_FDCANRST BIT(24) |
| 1369 | |
| 1370 | /* RCC_APB3RSTSETR register fields */ |
| 1371 | #define RCC_APB3RSTSETR_LPTIM2RST BIT(0) |
| 1372 | #define RCC_APB3RSTSETR_LPTIM3RST BIT(1) |
| 1373 | #define RCC_APB3RSTSETR_LPTIM4RST BIT(2) |
| 1374 | #define RCC_APB3RSTSETR_LPTIM5RST BIT(3) |
| 1375 | #define RCC_APB3RSTSETR_SAI4RST BIT(8) |
| 1376 | #define RCC_APB3RSTSETR_SYSCFGRST BIT(11) |
| 1377 | #define RCC_APB3RSTSETR_VREFRST BIT(13) |
| 1378 | #define RCC_APB3RSTSETR_TMPSENSRST BIT(16) |
| 1379 | #define RCC_APB3RSTSETR_PMBCTRLRST BIT(17) |
| 1380 | |
| 1381 | /* RCC_APB3RSTCLRR register fields */ |
| 1382 | #define RCC_APB3RSTCLRR_LPTIM2RST BIT(0) |
| 1383 | #define RCC_APB3RSTCLRR_LPTIM3RST BIT(1) |
| 1384 | #define RCC_APB3RSTCLRR_LPTIM4RST BIT(2) |
| 1385 | #define RCC_APB3RSTCLRR_LPTIM5RST BIT(3) |
| 1386 | #define RCC_APB3RSTCLRR_SAI4RST BIT(8) |
| 1387 | #define RCC_APB3RSTCLRR_SYSCFGRST BIT(11) |
| 1388 | #define RCC_APB3RSTCLRR_VREFRST BIT(13) |
| 1389 | #define RCC_APB3RSTCLRR_TMPSENSRST BIT(16) |
| 1390 | #define RCC_APB3RSTCLRR_PMBCTRLRST BIT(17) |
| 1391 | |
| 1392 | /* RCC_AHB2RSTSETR register fields */ |
| 1393 | #define RCC_AHB2RSTSETR_DMA1RST BIT(0) |
| 1394 | #define RCC_AHB2RSTSETR_DMA2RST BIT(1) |
| 1395 | #define RCC_AHB2RSTSETR_DMAMUXRST BIT(2) |
| 1396 | #define RCC_AHB2RSTSETR_ADC12RST BIT(5) |
| 1397 | #define RCC_AHB2RSTSETR_USBORST BIT(8) |
| 1398 | #define RCC_AHB2RSTSETR_SDMMC3RST BIT(16) |
| 1399 | |
| 1400 | /* RCC_AHB2RSTCLRR register fields */ |
| 1401 | #define RCC_AHB2RSTCLRR_DMA1RST BIT(0) |
| 1402 | #define RCC_AHB2RSTCLRR_DMA2RST BIT(1) |
| 1403 | #define RCC_AHB2RSTCLRR_DMAMUXRST BIT(2) |
| 1404 | #define RCC_AHB2RSTCLRR_ADC12RST BIT(5) |
| 1405 | #define RCC_AHB2RSTCLRR_USBORST BIT(8) |
| 1406 | #define RCC_AHB2RSTCLRR_SDMMC3RST BIT(16) |
| 1407 | |
| 1408 | /* RCC_AHB3RSTSETR register fields */ |
| 1409 | #define RCC_AHB3RSTSETR_DCMIRST BIT(0) |
| 1410 | #define RCC_AHB3RSTSETR_CRYP2RST BIT(4) |
| 1411 | #define RCC_AHB3RSTSETR_HASH2RST BIT(5) |
| 1412 | #define RCC_AHB3RSTSETR_RNG2RST BIT(6) |
| 1413 | #define RCC_AHB3RSTSETR_CRC2RST BIT(7) |
| 1414 | #define RCC_AHB3RSTSETR_HSEMRST BIT(11) |
| 1415 | #define RCC_AHB3RSTSETR_IPCCRST BIT(12) |
| 1416 | |
| 1417 | /* RCC_AHB3RSTCLRR register fields */ |
| 1418 | #define RCC_AHB3RSTCLRR_DCMIRST BIT(0) |
| 1419 | #define RCC_AHB3RSTCLRR_CRYP2RST BIT(4) |
| 1420 | #define RCC_AHB3RSTCLRR_HASH2RST BIT(5) |
| 1421 | #define RCC_AHB3RSTCLRR_RNG2RST BIT(6) |
| 1422 | #define RCC_AHB3RSTCLRR_CRC2RST BIT(7) |
| 1423 | #define RCC_AHB3RSTCLRR_HSEMRST BIT(11) |
| 1424 | #define RCC_AHB3RSTCLRR_IPCCRST BIT(12) |
| 1425 | |
| 1426 | /* RCC_AHB4RSTSETR register fields */ |
| 1427 | #define RCC_AHB4RSTSETR_GPIOARST BIT(0) |
| 1428 | #define RCC_AHB4RSTSETR_GPIOBRST BIT(1) |
| 1429 | #define RCC_AHB4RSTSETR_GPIOCRST BIT(2) |
| 1430 | #define RCC_AHB4RSTSETR_GPIODRST BIT(3) |
| 1431 | #define RCC_AHB4RSTSETR_GPIOERST BIT(4) |
| 1432 | #define RCC_AHB4RSTSETR_GPIOFRST BIT(5) |
| 1433 | #define RCC_AHB4RSTSETR_GPIOGRST BIT(6) |
| 1434 | #define RCC_AHB4RSTSETR_GPIOHRST BIT(7) |
| 1435 | #define RCC_AHB4RSTSETR_GPIOIRST BIT(8) |
| 1436 | #define RCC_AHB4RSTSETR_GPIOJRST BIT(9) |
| 1437 | #define RCC_AHB4RSTSETR_GPIOKRST BIT(10) |
| 1438 | |
| 1439 | /* RCC_AHB4RSTCLRR register fields */ |
| 1440 | #define RCC_AHB4RSTCLRR_GPIOARST BIT(0) |
| 1441 | #define RCC_AHB4RSTCLRR_GPIOBRST BIT(1) |
| 1442 | #define RCC_AHB4RSTCLRR_GPIOCRST BIT(2) |
| 1443 | #define RCC_AHB4RSTCLRR_GPIODRST BIT(3) |
| 1444 | #define RCC_AHB4RSTCLRR_GPIOERST BIT(4) |
| 1445 | #define RCC_AHB4RSTCLRR_GPIOFRST BIT(5) |
| 1446 | #define RCC_AHB4RSTCLRR_GPIOGRST BIT(6) |
| 1447 | #define RCC_AHB4RSTCLRR_GPIOHRST BIT(7) |
| 1448 | #define RCC_AHB4RSTCLRR_GPIOIRST BIT(8) |
| 1449 | #define RCC_AHB4RSTCLRR_GPIOJRST BIT(9) |
| 1450 | #define RCC_AHB4RSTCLRR_GPIOKRST BIT(10) |
| 1451 | |
| 1452 | /* RCC_MP_APB1ENSETR register fields */ |
| 1453 | #define RCC_MP_APB1ENSETR_TIM2EN BIT(0) |
| 1454 | #define RCC_MP_APB1ENSETR_TIM3EN BIT(1) |
| 1455 | #define RCC_MP_APB1ENSETR_TIM4EN BIT(2) |
| 1456 | #define RCC_MP_APB1ENSETR_TIM5EN BIT(3) |
| 1457 | #define RCC_MP_APB1ENSETR_TIM6EN BIT(4) |
| 1458 | #define RCC_MP_APB1ENSETR_TIM7EN BIT(5) |
| 1459 | #define RCC_MP_APB1ENSETR_TIM12EN BIT(6) |
| 1460 | #define RCC_MP_APB1ENSETR_TIM13EN BIT(7) |
| 1461 | #define RCC_MP_APB1ENSETR_TIM14EN BIT(8) |
| 1462 | #define RCC_MP_APB1ENSETR_LPTIM1EN BIT(9) |
| 1463 | #define RCC_MP_APB1ENSETR_SPI2EN BIT(11) |
| 1464 | #define RCC_MP_APB1ENSETR_SPI3EN BIT(12) |
| 1465 | #define RCC_MP_APB1ENSETR_USART2EN BIT(14) |
| 1466 | #define RCC_MP_APB1ENSETR_USART3EN BIT(15) |
| 1467 | #define RCC_MP_APB1ENSETR_UART4EN BIT(16) |
| 1468 | #define RCC_MP_APB1ENSETR_UART5EN BIT(17) |
| 1469 | #define RCC_MP_APB1ENSETR_UART7EN BIT(18) |
| 1470 | #define RCC_MP_APB1ENSETR_UART8EN BIT(19) |
| 1471 | #define RCC_MP_APB1ENSETR_I2C1EN BIT(21) |
| 1472 | #define RCC_MP_APB1ENSETR_I2C2EN BIT(22) |
| 1473 | #define RCC_MP_APB1ENSETR_I2C3EN BIT(23) |
| 1474 | #define RCC_MP_APB1ENSETR_I2C5EN BIT(24) |
| 1475 | #define RCC_MP_APB1ENSETR_SPDIFEN BIT(26) |
| 1476 | #define RCC_MP_APB1ENSETR_CECEN BIT(27) |
| 1477 | #define RCC_MP_APB1ENSETR_DAC12EN BIT(29) |
| 1478 | #define RCC_MP_APB1ENSETR_MDIOSEN BIT(31) |
| 1479 | |
| 1480 | /* RCC_MP_APB1ENCLRR register fields */ |
| 1481 | #define RCC_MP_APB1ENCLRR_TIM2EN BIT(0) |
| 1482 | #define RCC_MP_APB1ENCLRR_TIM3EN BIT(1) |
| 1483 | #define RCC_MP_APB1ENCLRR_TIM4EN BIT(2) |
| 1484 | #define RCC_MP_APB1ENCLRR_TIM5EN BIT(3) |
| 1485 | #define RCC_MP_APB1ENCLRR_TIM6EN BIT(4) |
| 1486 | #define RCC_MP_APB1ENCLRR_TIM7EN BIT(5) |
| 1487 | #define RCC_MP_APB1ENCLRR_TIM12EN BIT(6) |
| 1488 | #define RCC_MP_APB1ENCLRR_TIM13EN BIT(7) |
| 1489 | #define RCC_MP_APB1ENCLRR_TIM14EN BIT(8) |
| 1490 | #define RCC_MP_APB1ENCLRR_LPTIM1EN BIT(9) |
| 1491 | #define RCC_MP_APB1ENCLRR_SPI2EN BIT(11) |
| 1492 | #define RCC_MP_APB1ENCLRR_SPI3EN BIT(12) |
| 1493 | #define RCC_MP_APB1ENCLRR_USART2EN BIT(14) |
| 1494 | #define RCC_MP_APB1ENCLRR_USART3EN BIT(15) |
| 1495 | #define RCC_MP_APB1ENCLRR_UART4EN BIT(16) |
| 1496 | #define RCC_MP_APB1ENCLRR_UART5EN BIT(17) |
| 1497 | #define RCC_MP_APB1ENCLRR_UART7EN BIT(18) |
| 1498 | #define RCC_MP_APB1ENCLRR_UART8EN BIT(19) |
| 1499 | #define RCC_MP_APB1ENCLRR_I2C1EN BIT(21) |
| 1500 | #define RCC_MP_APB1ENCLRR_I2C2EN BIT(22) |
| 1501 | #define RCC_MP_APB1ENCLRR_I2C3EN BIT(23) |
| 1502 | #define RCC_MP_APB1ENCLRR_I2C5EN BIT(24) |
| 1503 | #define RCC_MP_APB1ENCLRR_SPDIFEN BIT(26) |
| 1504 | #define RCC_MP_APB1ENCLRR_CECEN BIT(27) |
| 1505 | #define RCC_MP_APB1ENCLRR_DAC12EN BIT(29) |
| 1506 | #define RCC_MP_APB1ENCLRR_MDIOSEN BIT(31) |
| 1507 | |
| 1508 | /* RCC_MP_APB2ENSETR register fields */ |
| 1509 | #define RCC_MP_APB2ENSETR_TIM1EN BIT(0) |
| 1510 | #define RCC_MP_APB2ENSETR_TIM8EN BIT(1) |
| 1511 | #define RCC_MP_APB2ENSETR_TIM15EN BIT(2) |
| 1512 | #define RCC_MP_APB2ENSETR_TIM16EN BIT(3) |
| 1513 | #define RCC_MP_APB2ENSETR_TIM17EN BIT(4) |
| 1514 | #define RCC_MP_APB2ENSETR_SPI1EN BIT(8) |
| 1515 | #define RCC_MP_APB2ENSETR_SPI4EN BIT(9) |
| 1516 | #define RCC_MP_APB2ENSETR_SPI5EN BIT(10) |
| 1517 | #define RCC_MP_APB2ENSETR_USART6EN BIT(13) |
| 1518 | #define RCC_MP_APB2ENSETR_SAI1EN BIT(16) |
| 1519 | #define RCC_MP_APB2ENSETR_SAI2EN BIT(17) |
| 1520 | #define RCC_MP_APB2ENSETR_SAI3EN BIT(18) |
| 1521 | #define RCC_MP_APB2ENSETR_DFSDMEN BIT(20) |
| 1522 | #define RCC_MP_APB2ENSETR_ADFSDMEN BIT(21) |
| 1523 | #define RCC_MP_APB2ENSETR_FDCANEN BIT(24) |
| 1524 | |
| 1525 | /* RCC_MP_APB2ENCLRR register fields */ |
| 1526 | #define RCC_MP_APB2ENCLRR_TIM1EN BIT(0) |
| 1527 | #define RCC_MP_APB2ENCLRR_TIM8EN BIT(1) |
| 1528 | #define RCC_MP_APB2ENCLRR_TIM15EN BIT(2) |
| 1529 | #define RCC_MP_APB2ENCLRR_TIM16EN BIT(3) |
| 1530 | #define RCC_MP_APB2ENCLRR_TIM17EN BIT(4) |
| 1531 | #define RCC_MP_APB2ENCLRR_SPI1EN BIT(8) |
| 1532 | #define RCC_MP_APB2ENCLRR_SPI4EN BIT(9) |
| 1533 | #define RCC_MP_APB2ENCLRR_SPI5EN BIT(10) |
| 1534 | #define RCC_MP_APB2ENCLRR_USART6EN BIT(13) |
| 1535 | #define RCC_MP_APB2ENCLRR_SAI1EN BIT(16) |
| 1536 | #define RCC_MP_APB2ENCLRR_SAI2EN BIT(17) |
| 1537 | #define RCC_MP_APB2ENCLRR_SAI3EN BIT(18) |
| 1538 | #define RCC_MP_APB2ENCLRR_DFSDMEN BIT(20) |
| 1539 | #define RCC_MP_APB2ENCLRR_ADFSDMEN BIT(21) |
| 1540 | #define RCC_MP_APB2ENCLRR_FDCANEN BIT(24) |
| 1541 | |
| 1542 | /* RCC_MP_APB3ENSETR register fields */ |
| 1543 | #define RCC_MP_APB3ENSETR_LPTIM2EN BIT(0) |
| 1544 | #define RCC_MP_APB3ENSETR_LPTIM3EN BIT(1) |
| 1545 | #define RCC_MP_APB3ENSETR_LPTIM4EN BIT(2) |
| 1546 | #define RCC_MP_APB3ENSETR_LPTIM5EN BIT(3) |
| 1547 | #define RCC_MP_APB3ENSETR_SAI4EN BIT(8) |
| 1548 | #define RCC_MP_APB3ENSETR_SYSCFGEN BIT(11) |
| 1549 | #define RCC_MP_APB3ENSETR_VREFEN BIT(13) |
| 1550 | #define RCC_MP_APB3ENSETR_TMPSENSEN BIT(16) |
| 1551 | #define RCC_MP_APB3ENSETR_PMBCTRLEN BIT(17) |
| 1552 | #define RCC_MP_APB3ENSETR_HDPEN BIT(20) |
| 1553 | |
| 1554 | /* RCC_MP_APB3ENCLRR register fields */ |
| 1555 | #define RCC_MP_APB3ENCLRR_LPTIM2EN BIT(0) |
| 1556 | #define RCC_MP_APB3ENCLRR_LPTIM3EN BIT(1) |
| 1557 | #define RCC_MP_APB3ENCLRR_LPTIM4EN BIT(2) |
| 1558 | #define RCC_MP_APB3ENCLRR_LPTIM5EN BIT(3) |
| 1559 | #define RCC_MP_APB3ENCLRR_SAI4EN BIT(8) |
| 1560 | #define RCC_MP_APB3ENCLRR_SYSCFGEN BIT(11) |
| 1561 | #define RCC_MP_APB3ENCLRR_VREFEN BIT(13) |
| 1562 | #define RCC_MP_APB3ENCLRR_TMPSENSEN BIT(16) |
| 1563 | #define RCC_MP_APB3ENCLRR_PMBCTRLEN BIT(17) |
| 1564 | #define RCC_MP_APB3ENCLRR_HDPEN BIT(20) |
| 1565 | |
| 1566 | /* RCC_MP_AHB2ENSETR register fields */ |
| 1567 | #define RCC_MP_AHB2ENSETR_DMA1EN BIT(0) |
| 1568 | #define RCC_MP_AHB2ENSETR_DMA2EN BIT(1) |
| 1569 | #define RCC_MP_AHB2ENSETR_DMAMUXEN BIT(2) |
| 1570 | #define RCC_MP_AHB2ENSETR_ADC12EN BIT(5) |
| 1571 | #define RCC_MP_AHB2ENSETR_USBOEN BIT(8) |
| 1572 | #define RCC_MP_AHB2ENSETR_SDMMC3EN BIT(16) |
| 1573 | |
| 1574 | /* RCC_MP_AHB2ENCLRR register fields */ |
| 1575 | #define RCC_MP_AHB2ENCLRR_DMA1EN BIT(0) |
| 1576 | #define RCC_MP_AHB2ENCLRR_DMA2EN BIT(1) |
| 1577 | #define RCC_MP_AHB2ENCLRR_DMAMUXEN BIT(2) |
| 1578 | #define RCC_MP_AHB2ENCLRR_ADC12EN BIT(5) |
| 1579 | #define RCC_MP_AHB2ENCLRR_USBOEN BIT(8) |
| 1580 | #define RCC_MP_AHB2ENCLRR_SDMMC3EN BIT(16) |
| 1581 | |
| 1582 | /* RCC_MP_AHB3ENSETR register fields */ |
| 1583 | #define RCC_MP_AHB3ENSETR_DCMIEN BIT(0) |
| 1584 | #define RCC_MP_AHB3ENSETR_CRYP2EN BIT(4) |
| 1585 | #define RCC_MP_AHB3ENSETR_HASH2EN BIT(5) |
| 1586 | #define RCC_MP_AHB3ENSETR_RNG2EN BIT(6) |
| 1587 | #define RCC_MP_AHB3ENSETR_CRC2EN BIT(7) |
| 1588 | #define RCC_MP_AHB3ENSETR_HSEMEN BIT(11) |
| 1589 | #define RCC_MP_AHB3ENSETR_IPCCEN BIT(12) |
| 1590 | |
| 1591 | /* RCC_MP_AHB3ENCLRR register fields */ |
| 1592 | #define RCC_MP_AHB3ENCLRR_DCMIEN BIT(0) |
| 1593 | #define RCC_MP_AHB3ENCLRR_CRYP2EN BIT(4) |
| 1594 | #define RCC_MP_AHB3ENCLRR_HASH2EN BIT(5) |
| 1595 | #define RCC_MP_AHB3ENCLRR_RNG2EN BIT(6) |
| 1596 | #define RCC_MP_AHB3ENCLRR_CRC2EN BIT(7) |
| 1597 | #define RCC_MP_AHB3ENCLRR_HSEMEN BIT(11) |
| 1598 | #define RCC_MP_AHB3ENCLRR_IPCCEN BIT(12) |
| 1599 | |
| 1600 | /* RCC_MP_AHB4ENSETR register fields */ |
| 1601 | #define RCC_MP_AHB4ENSETR_GPIOAEN BIT(0) |
| 1602 | #define RCC_MP_AHB4ENSETR_GPIOBEN BIT(1) |
| 1603 | #define RCC_MP_AHB4ENSETR_GPIOCEN BIT(2) |
| 1604 | #define RCC_MP_AHB4ENSETR_GPIODEN BIT(3) |
| 1605 | #define RCC_MP_AHB4ENSETR_GPIOEEN BIT(4) |
| 1606 | #define RCC_MP_AHB4ENSETR_GPIOFEN BIT(5) |
| 1607 | #define RCC_MP_AHB4ENSETR_GPIOGEN BIT(6) |
| 1608 | #define RCC_MP_AHB4ENSETR_GPIOHEN BIT(7) |
| 1609 | #define RCC_MP_AHB4ENSETR_GPIOIEN BIT(8) |
| 1610 | #define RCC_MP_AHB4ENSETR_GPIOJEN BIT(9) |
| 1611 | #define RCC_MP_AHB4ENSETR_GPIOKEN BIT(10) |
| 1612 | |
| 1613 | /* RCC_MP_AHB4ENCLRR register fields */ |
| 1614 | #define RCC_MP_AHB4ENCLRR_GPIOAEN BIT(0) |
| 1615 | #define RCC_MP_AHB4ENCLRR_GPIOBEN BIT(1) |
| 1616 | #define RCC_MP_AHB4ENCLRR_GPIOCEN BIT(2) |
| 1617 | #define RCC_MP_AHB4ENCLRR_GPIODEN BIT(3) |
| 1618 | #define RCC_MP_AHB4ENCLRR_GPIOEEN BIT(4) |
| 1619 | #define RCC_MP_AHB4ENCLRR_GPIOFEN BIT(5) |
| 1620 | #define RCC_MP_AHB4ENCLRR_GPIOGEN BIT(6) |
| 1621 | #define RCC_MP_AHB4ENCLRR_GPIOHEN BIT(7) |
| 1622 | #define RCC_MP_AHB4ENCLRR_GPIOIEN BIT(8) |
| 1623 | #define RCC_MP_AHB4ENCLRR_GPIOJEN BIT(9) |
| 1624 | #define RCC_MP_AHB4ENCLRR_GPIOKEN BIT(10) |
| 1625 | |
| 1626 | /* RCC_MP_MLAHBENSETR register fields */ |
| 1627 | #define RCC_MP_MLAHBENSETR_RETRAMEN BIT(4) |
| 1628 | |
| 1629 | /* RCC_MP_MLAHBENCLRR register fields */ |
| 1630 | #define RCC_MP_MLAHBENCLRR_RETRAMEN BIT(4) |
| 1631 | |
| 1632 | /* RCC_MC_APB1ENSETR register fields */ |
| 1633 | #define RCC_MC_APB1ENSETR_TIM2EN BIT(0) |
| 1634 | #define RCC_MC_APB1ENSETR_TIM3EN BIT(1) |
| 1635 | #define RCC_MC_APB1ENSETR_TIM4EN BIT(2) |
| 1636 | #define RCC_MC_APB1ENSETR_TIM5EN BIT(3) |
| 1637 | #define RCC_MC_APB1ENSETR_TIM6EN BIT(4) |
| 1638 | #define RCC_MC_APB1ENSETR_TIM7EN BIT(5) |
| 1639 | #define RCC_MC_APB1ENSETR_TIM12EN BIT(6) |
| 1640 | #define RCC_MC_APB1ENSETR_TIM13EN BIT(7) |
| 1641 | #define RCC_MC_APB1ENSETR_TIM14EN BIT(8) |
| 1642 | #define RCC_MC_APB1ENSETR_LPTIM1EN BIT(9) |
| 1643 | #define RCC_MC_APB1ENSETR_SPI2EN BIT(11) |
| 1644 | #define RCC_MC_APB1ENSETR_SPI3EN BIT(12) |
| 1645 | #define RCC_MC_APB1ENSETR_USART2EN BIT(14) |
| 1646 | #define RCC_MC_APB1ENSETR_USART3EN BIT(15) |
| 1647 | #define RCC_MC_APB1ENSETR_UART4EN BIT(16) |
| 1648 | #define RCC_MC_APB1ENSETR_UART5EN BIT(17) |
| 1649 | #define RCC_MC_APB1ENSETR_UART7EN BIT(18) |
| 1650 | #define RCC_MC_APB1ENSETR_UART8EN BIT(19) |
| 1651 | #define RCC_MC_APB1ENSETR_I2C1EN BIT(21) |
| 1652 | #define RCC_MC_APB1ENSETR_I2C2EN BIT(22) |
| 1653 | #define RCC_MC_APB1ENSETR_I2C3EN BIT(23) |
| 1654 | #define RCC_MC_APB1ENSETR_I2C5EN BIT(24) |
| 1655 | #define RCC_MC_APB1ENSETR_SPDIFEN BIT(26) |
| 1656 | #define RCC_MC_APB1ENSETR_CECEN BIT(27) |
| 1657 | #define RCC_MC_APB1ENSETR_WWDG1EN BIT(28) |
| 1658 | #define RCC_MC_APB1ENSETR_DAC12EN BIT(29) |
| 1659 | #define RCC_MC_APB1ENSETR_MDIOSEN BIT(31) |
| 1660 | |
| 1661 | /* RCC_MC_APB1ENCLRR register fields */ |
| 1662 | #define RCC_MC_APB1ENCLRR_TIM2EN BIT(0) |
| 1663 | #define RCC_MC_APB1ENCLRR_TIM3EN BIT(1) |
| 1664 | #define RCC_MC_APB1ENCLRR_TIM4EN BIT(2) |
| 1665 | #define RCC_MC_APB1ENCLRR_TIM5EN BIT(3) |
| 1666 | #define RCC_MC_APB1ENCLRR_TIM6EN BIT(4) |
| 1667 | #define RCC_MC_APB1ENCLRR_TIM7EN BIT(5) |
| 1668 | #define RCC_MC_APB1ENCLRR_TIM12EN BIT(6) |
| 1669 | #define RCC_MC_APB1ENCLRR_TIM13EN BIT(7) |
| 1670 | #define RCC_MC_APB1ENCLRR_TIM14EN BIT(8) |
| 1671 | #define RCC_MC_APB1ENCLRR_LPTIM1EN BIT(9) |
| 1672 | #define RCC_MC_APB1ENCLRR_SPI2EN BIT(11) |
| 1673 | #define RCC_MC_APB1ENCLRR_SPI3EN BIT(12) |
| 1674 | #define RCC_MC_APB1ENCLRR_USART2EN BIT(14) |
| 1675 | #define RCC_MC_APB1ENCLRR_USART3EN BIT(15) |
| 1676 | #define RCC_MC_APB1ENCLRR_UART4EN BIT(16) |
| 1677 | #define RCC_MC_APB1ENCLRR_UART5EN BIT(17) |
| 1678 | #define RCC_MC_APB1ENCLRR_UART7EN BIT(18) |
| 1679 | #define RCC_MC_APB1ENCLRR_UART8EN BIT(19) |
| 1680 | #define RCC_MC_APB1ENCLRR_I2C1EN BIT(21) |
| 1681 | #define RCC_MC_APB1ENCLRR_I2C2EN BIT(22) |
| 1682 | #define RCC_MC_APB1ENCLRR_I2C3EN BIT(23) |
| 1683 | #define RCC_MC_APB1ENCLRR_I2C5EN BIT(24) |
| 1684 | #define RCC_MC_APB1ENCLRR_SPDIFEN BIT(26) |
| 1685 | #define RCC_MC_APB1ENCLRR_CECEN BIT(27) |
| 1686 | #define RCC_MC_APB1ENCLRR_DAC12EN BIT(29) |
| 1687 | #define RCC_MC_APB1ENCLRR_MDIOSEN BIT(31) |
| 1688 | |
| 1689 | /* RCC_MC_APB2ENSETR register fields */ |
| 1690 | #define RCC_MC_APB2ENSETR_TIM1EN BIT(0) |
| 1691 | #define RCC_MC_APB2ENSETR_TIM8EN BIT(1) |
| 1692 | #define RCC_MC_APB2ENSETR_TIM15EN BIT(2) |
| 1693 | #define RCC_MC_APB2ENSETR_TIM16EN BIT(3) |
| 1694 | #define RCC_MC_APB2ENSETR_TIM17EN BIT(4) |
| 1695 | #define RCC_MC_APB2ENSETR_SPI1EN BIT(8) |
| 1696 | #define RCC_MC_APB2ENSETR_SPI4EN BIT(9) |
| 1697 | #define RCC_MC_APB2ENSETR_SPI5EN BIT(10) |
| 1698 | #define RCC_MC_APB2ENSETR_USART6EN BIT(13) |
| 1699 | #define RCC_MC_APB2ENSETR_SAI1EN BIT(16) |
| 1700 | #define RCC_MC_APB2ENSETR_SAI2EN BIT(17) |
| 1701 | #define RCC_MC_APB2ENSETR_SAI3EN BIT(18) |
| 1702 | #define RCC_MC_APB2ENSETR_DFSDMEN BIT(20) |
| 1703 | #define RCC_MC_APB2ENSETR_ADFSDMEN BIT(21) |
| 1704 | #define RCC_MC_APB2ENSETR_FDCANEN BIT(24) |
| 1705 | |
| 1706 | /* RCC_MC_APB2ENCLRR register fields */ |
| 1707 | #define RCC_MC_APB2ENCLRR_TIM1EN BIT(0) |
| 1708 | #define RCC_MC_APB2ENCLRR_TIM8EN BIT(1) |
| 1709 | #define RCC_MC_APB2ENCLRR_TIM15EN BIT(2) |
| 1710 | #define RCC_MC_APB2ENCLRR_TIM16EN BIT(3) |
| 1711 | #define RCC_MC_APB2ENCLRR_TIM17EN BIT(4) |
| 1712 | #define RCC_MC_APB2ENCLRR_SPI1EN BIT(8) |
| 1713 | #define RCC_MC_APB2ENCLRR_SPI4EN BIT(9) |
| 1714 | #define RCC_MC_APB2ENCLRR_SPI5EN BIT(10) |
| 1715 | #define RCC_MC_APB2ENCLRR_USART6EN BIT(13) |
| 1716 | #define RCC_MC_APB2ENCLRR_SAI1EN BIT(16) |
| 1717 | #define RCC_MC_APB2ENCLRR_SAI2EN BIT(17) |
| 1718 | #define RCC_MC_APB2ENCLRR_SAI3EN BIT(18) |
| 1719 | #define RCC_MC_APB2ENCLRR_DFSDMEN BIT(20) |
| 1720 | #define RCC_MC_APB2ENCLRR_ADFSDMEN BIT(21) |
| 1721 | #define RCC_MC_APB2ENCLRR_FDCANEN BIT(24) |
| 1722 | |
| 1723 | /* RCC_MC_APB3ENSETR register fields */ |
| 1724 | #define RCC_MC_APB3ENSETR_LPTIM2EN BIT(0) |
| 1725 | #define RCC_MC_APB3ENSETR_LPTIM3EN BIT(1) |
| 1726 | #define RCC_MC_APB3ENSETR_LPTIM4EN BIT(2) |
| 1727 | #define RCC_MC_APB3ENSETR_LPTIM5EN BIT(3) |
| 1728 | #define RCC_MC_APB3ENSETR_SAI4EN BIT(8) |
| 1729 | #define RCC_MC_APB3ENSETR_SYSCFGEN BIT(11) |
| 1730 | #define RCC_MC_APB3ENSETR_VREFEN BIT(13) |
| 1731 | #define RCC_MC_APB3ENSETR_TMPSENSEN BIT(16) |
| 1732 | #define RCC_MC_APB3ENSETR_PMBCTRLEN BIT(17) |
| 1733 | #define RCC_MC_APB3ENSETR_HDPEN BIT(20) |
| 1734 | |
| 1735 | /* RCC_MC_APB3ENCLRR register fields */ |
| 1736 | #define RCC_MC_APB3ENCLRR_LPTIM2EN BIT(0) |
| 1737 | #define RCC_MC_APB3ENCLRR_LPTIM3EN BIT(1) |
| 1738 | #define RCC_MC_APB3ENCLRR_LPTIM4EN BIT(2) |
| 1739 | #define RCC_MC_APB3ENCLRR_LPTIM5EN BIT(3) |
| 1740 | #define RCC_MC_APB3ENCLRR_SAI4EN BIT(8) |
| 1741 | #define RCC_MC_APB3ENCLRR_SYSCFGEN BIT(11) |
| 1742 | #define RCC_MC_APB3ENCLRR_VREFEN BIT(13) |
| 1743 | #define RCC_MC_APB3ENCLRR_TMPSENSEN BIT(16) |
| 1744 | #define RCC_MC_APB3ENCLRR_PMBCTRLEN BIT(17) |
| 1745 | #define RCC_MC_APB3ENCLRR_HDPEN BIT(20) |
| 1746 | |
| 1747 | /* RCC_MC_AHB2ENSETR register fields */ |
| 1748 | #define RCC_MC_AHB2ENSETR_DMA1EN BIT(0) |
| 1749 | #define RCC_MC_AHB2ENSETR_DMA2EN BIT(1) |
| 1750 | #define RCC_MC_AHB2ENSETR_DMAMUXEN BIT(2) |
| 1751 | #define RCC_MC_AHB2ENSETR_ADC12EN BIT(5) |
| 1752 | #define RCC_MC_AHB2ENSETR_USBOEN BIT(8) |
| 1753 | #define RCC_MC_AHB2ENSETR_SDMMC3EN BIT(16) |
| 1754 | |
| 1755 | /* RCC_MC_AHB2ENCLRR register fields */ |
| 1756 | #define RCC_MC_AHB2ENCLRR_DMA1EN BIT(0) |
| 1757 | #define RCC_MC_AHB2ENCLRR_DMA2EN BIT(1) |
| 1758 | #define RCC_MC_AHB2ENCLRR_DMAMUXEN BIT(2) |
| 1759 | #define RCC_MC_AHB2ENCLRR_ADC12EN BIT(5) |
| 1760 | #define RCC_MC_AHB2ENCLRR_USBOEN BIT(8) |
| 1761 | #define RCC_MC_AHB2ENCLRR_SDMMC3EN BIT(16) |
| 1762 | |
| 1763 | /* RCC_MC_AHB3ENSETR register fields */ |
| 1764 | #define RCC_MC_AHB3ENSETR_DCMIEN BIT(0) |
| 1765 | #define RCC_MC_AHB3ENSETR_CRYP2EN BIT(4) |
| 1766 | #define RCC_MC_AHB3ENSETR_HASH2EN BIT(5) |
| 1767 | #define RCC_MC_AHB3ENSETR_RNG2EN BIT(6) |
| 1768 | #define RCC_MC_AHB3ENSETR_CRC2EN BIT(7) |
| 1769 | #define RCC_MC_AHB3ENSETR_HSEMEN BIT(11) |
| 1770 | #define RCC_MC_AHB3ENSETR_IPCCEN BIT(12) |
| 1771 | |
| 1772 | /* RCC_MC_AHB3ENCLRR register fields */ |
| 1773 | #define RCC_MC_AHB3ENCLRR_DCMIEN BIT(0) |
| 1774 | #define RCC_MC_AHB3ENCLRR_CRYP2EN BIT(4) |
| 1775 | #define RCC_MC_AHB3ENCLRR_HASH2EN BIT(5) |
| 1776 | #define RCC_MC_AHB3ENCLRR_RNG2EN BIT(6) |
| 1777 | #define RCC_MC_AHB3ENCLRR_CRC2EN BIT(7) |
| 1778 | #define RCC_MC_AHB3ENCLRR_HSEMEN BIT(11) |
| 1779 | #define RCC_MC_AHB3ENCLRR_IPCCEN BIT(12) |
| 1780 | |
| 1781 | /* RCC_MC_AHB4ENSETR register fields */ |
| 1782 | #define RCC_MC_AHB4ENSETR_GPIOAEN BIT(0) |
| 1783 | #define RCC_MC_AHB4ENSETR_GPIOBEN BIT(1) |
| 1784 | #define RCC_MC_AHB4ENSETR_GPIOCEN BIT(2) |
| 1785 | #define RCC_MC_AHB4ENSETR_GPIODEN BIT(3) |
| 1786 | #define RCC_MC_AHB4ENSETR_GPIOEEN BIT(4) |
| 1787 | #define RCC_MC_AHB4ENSETR_GPIOFEN BIT(5) |
| 1788 | #define RCC_MC_AHB4ENSETR_GPIOGEN BIT(6) |
| 1789 | #define RCC_MC_AHB4ENSETR_GPIOHEN BIT(7) |
| 1790 | #define RCC_MC_AHB4ENSETR_GPIOIEN BIT(8) |
| 1791 | #define RCC_MC_AHB4ENSETR_GPIOJEN BIT(9) |
| 1792 | #define RCC_MC_AHB4ENSETR_GPIOKEN BIT(10) |
| 1793 | |
| 1794 | /* RCC_MC_AHB4ENCLRR register fields */ |
| 1795 | #define RCC_MC_AHB4ENCLRR_GPIOAEN BIT(0) |
| 1796 | #define RCC_MC_AHB4ENCLRR_GPIOBEN BIT(1) |
| 1797 | #define RCC_MC_AHB4ENCLRR_GPIOCEN BIT(2) |
| 1798 | #define RCC_MC_AHB4ENCLRR_GPIODEN BIT(3) |
| 1799 | #define RCC_MC_AHB4ENCLRR_GPIOEEN BIT(4) |
| 1800 | #define RCC_MC_AHB4ENCLRR_GPIOFEN BIT(5) |
| 1801 | #define RCC_MC_AHB4ENCLRR_GPIOGEN BIT(6) |
| 1802 | #define RCC_MC_AHB4ENCLRR_GPIOHEN BIT(7) |
| 1803 | #define RCC_MC_AHB4ENCLRR_GPIOIEN BIT(8) |
| 1804 | #define RCC_MC_AHB4ENCLRR_GPIOJEN BIT(9) |
| 1805 | #define RCC_MC_AHB4ENCLRR_GPIOKEN BIT(10) |
| 1806 | |
| 1807 | /* RCC_MC_AXIMENSETR register fields */ |
| 1808 | #define RCC_MC_AXIMENSETR_SYSRAMEN BIT(0) |
| 1809 | |
| 1810 | /* RCC_MC_AXIMENCLRR register fields */ |
| 1811 | #define RCC_MC_AXIMENCLRR_SYSRAMEN BIT(0) |
| 1812 | |
| 1813 | /* RCC_MC_MLAHBENSETR register fields */ |
| 1814 | #define RCC_MC_MLAHBENSETR_RETRAMEN BIT(4) |
| 1815 | |
| 1816 | /* RCC_MC_MLAHBENCLRR register fields */ |
| 1817 | #define RCC_MC_MLAHBENCLRR_RETRAMEN BIT(4) |
| 1818 | |
| 1819 | /* RCC_MP_APB1LPENSETR register fields */ |
| 1820 | #define RCC_MP_APB1LPENSETR_TIM2LPEN BIT(0) |
| 1821 | #define RCC_MP_APB1LPENSETR_TIM3LPEN BIT(1) |
| 1822 | #define RCC_MP_APB1LPENSETR_TIM4LPEN BIT(2) |
| 1823 | #define RCC_MP_APB1LPENSETR_TIM5LPEN BIT(3) |
| 1824 | #define RCC_MP_APB1LPENSETR_TIM6LPEN BIT(4) |
| 1825 | #define RCC_MP_APB1LPENSETR_TIM7LPEN BIT(5) |
| 1826 | #define RCC_MP_APB1LPENSETR_TIM12LPEN BIT(6) |
| 1827 | #define RCC_MP_APB1LPENSETR_TIM13LPEN BIT(7) |
| 1828 | #define RCC_MP_APB1LPENSETR_TIM14LPEN BIT(8) |
| 1829 | #define RCC_MP_APB1LPENSETR_LPTIM1LPEN BIT(9) |
| 1830 | #define RCC_MP_APB1LPENSETR_SPI2LPEN BIT(11) |
| 1831 | #define RCC_MP_APB1LPENSETR_SPI3LPEN BIT(12) |
| 1832 | #define RCC_MP_APB1LPENSETR_USART2LPEN BIT(14) |
| 1833 | #define RCC_MP_APB1LPENSETR_USART3LPEN BIT(15) |
| 1834 | #define RCC_MP_APB1LPENSETR_UART4LPEN BIT(16) |
| 1835 | #define RCC_MP_APB1LPENSETR_UART5LPEN BIT(17) |
| 1836 | #define RCC_MP_APB1LPENSETR_UART7LPEN BIT(18) |
| 1837 | #define RCC_MP_APB1LPENSETR_UART8LPEN BIT(19) |
| 1838 | #define RCC_MP_APB1LPENSETR_I2C1LPEN BIT(21) |
| 1839 | #define RCC_MP_APB1LPENSETR_I2C2LPEN BIT(22) |
| 1840 | #define RCC_MP_APB1LPENSETR_I2C3LPEN BIT(23) |
| 1841 | #define RCC_MP_APB1LPENSETR_I2C5LPEN BIT(24) |
| 1842 | #define RCC_MP_APB1LPENSETR_SPDIFLPEN BIT(26) |
| 1843 | #define RCC_MP_APB1LPENSETR_CECLPEN BIT(27) |
| 1844 | #define RCC_MP_APB1LPENSETR_DAC12LPEN BIT(29) |
| 1845 | #define RCC_MP_APB1LPENSETR_MDIOSLPEN BIT(31) |
| 1846 | |
| 1847 | /* RCC_MP_APB1LPENCLRR register fields */ |
| 1848 | #define RCC_MP_APB1LPENCLRR_TIM2LPEN BIT(0) |
| 1849 | #define RCC_MP_APB1LPENCLRR_TIM3LPEN BIT(1) |
| 1850 | #define RCC_MP_APB1LPENCLRR_TIM4LPEN BIT(2) |
| 1851 | #define RCC_MP_APB1LPENCLRR_TIM5LPEN BIT(3) |
| 1852 | #define RCC_MP_APB1LPENCLRR_TIM6LPEN BIT(4) |
| 1853 | #define RCC_MP_APB1LPENCLRR_TIM7LPEN BIT(5) |
| 1854 | #define RCC_MP_APB1LPENCLRR_TIM12LPEN BIT(6) |
| 1855 | #define RCC_MP_APB1LPENCLRR_TIM13LPEN BIT(7) |
| 1856 | #define RCC_MP_APB1LPENCLRR_TIM14LPEN BIT(8) |
| 1857 | #define RCC_MP_APB1LPENCLRR_LPTIM1LPEN BIT(9) |
| 1858 | #define RCC_MP_APB1LPENCLRR_SPI2LPEN BIT(11) |
| 1859 | #define RCC_MP_APB1LPENCLRR_SPI3LPEN BIT(12) |
| 1860 | #define RCC_MP_APB1LPENCLRR_USART2LPEN BIT(14) |
| 1861 | #define RCC_MP_APB1LPENCLRR_USART3LPEN BIT(15) |
| 1862 | #define RCC_MP_APB1LPENCLRR_UART4LPEN BIT(16) |
| 1863 | #define RCC_MP_APB1LPENCLRR_UART5LPEN BIT(17) |
| 1864 | #define RCC_MP_APB1LPENCLRR_UART7LPEN BIT(18) |
| 1865 | #define RCC_MP_APB1LPENCLRR_UART8LPEN BIT(19) |
| 1866 | #define RCC_MP_APB1LPENCLRR_I2C1LPEN BIT(21) |
| 1867 | #define RCC_MP_APB1LPENCLRR_I2C2LPEN BIT(22) |
| 1868 | #define RCC_MP_APB1LPENCLRR_I2C3LPEN BIT(23) |
| 1869 | #define RCC_MP_APB1LPENCLRR_I2C5LPEN BIT(24) |
| 1870 | #define RCC_MP_APB1LPENCLRR_SPDIFLPEN BIT(26) |
| 1871 | #define RCC_MP_APB1LPENCLRR_CECLPEN BIT(27) |
| 1872 | #define RCC_MP_APB1LPENCLRR_DAC12LPEN BIT(29) |
| 1873 | #define RCC_MP_APB1LPENCLRR_MDIOSLPEN BIT(31) |
| 1874 | |
| 1875 | /* RCC_MP_APB2LPENSETR register fields */ |
| 1876 | #define RCC_MP_APB2LPENSETR_TIM1LPEN BIT(0) |
| 1877 | #define RCC_MP_APB2LPENSETR_TIM8LPEN BIT(1) |
| 1878 | #define RCC_MP_APB2LPENSETR_TIM15LPEN BIT(2) |
| 1879 | #define RCC_MP_APB2LPENSETR_TIM16LPEN BIT(3) |
| 1880 | #define RCC_MP_APB2LPENSETR_TIM17LPEN BIT(4) |
| 1881 | #define RCC_MP_APB2LPENSETR_SPI1LPEN BIT(8) |
| 1882 | #define RCC_MP_APB2LPENSETR_SPI4LPEN BIT(9) |
| 1883 | #define RCC_MP_APB2LPENSETR_SPI5LPEN BIT(10) |
| 1884 | #define RCC_MP_APB2LPENSETR_USART6LPEN BIT(13) |
| 1885 | #define RCC_MP_APB2LPENSETR_SAI1LPEN BIT(16) |
| 1886 | #define RCC_MP_APB2LPENSETR_SAI2LPEN BIT(17) |
| 1887 | #define RCC_MP_APB2LPENSETR_SAI3LPEN BIT(18) |
| 1888 | #define RCC_MP_APB2LPENSETR_DFSDMLPEN BIT(20) |
| 1889 | #define RCC_MP_APB2LPENSETR_ADFSDMLPEN BIT(21) |
| 1890 | #define RCC_MP_APB2LPENSETR_FDCANLPEN BIT(24) |
| 1891 | |
| 1892 | /* RCC_MP_APB2LPENCLRR register fields */ |
| 1893 | #define RCC_MP_APB2LPENCLRR_TIM1LPEN BIT(0) |
| 1894 | #define RCC_MP_APB2LPENCLRR_TIM8LPEN BIT(1) |
| 1895 | #define RCC_MP_APB2LPENCLRR_TIM15LPEN BIT(2) |
| 1896 | #define RCC_MP_APB2LPENCLRR_TIM16LPEN BIT(3) |
| 1897 | #define RCC_MP_APB2LPENCLRR_TIM17LPEN BIT(4) |
| 1898 | #define RCC_MP_APB2LPENCLRR_SPI1LPEN BIT(8) |
| 1899 | #define RCC_MP_APB2LPENCLRR_SPI4LPEN BIT(9) |
| 1900 | #define RCC_MP_APB2LPENCLRR_SPI5LPEN BIT(10) |
| 1901 | #define RCC_MP_APB2LPENCLRR_USART6LPEN BIT(13) |
| 1902 | #define RCC_MP_APB2LPENCLRR_SAI1LPEN BIT(16) |
| 1903 | #define RCC_MP_APB2LPENCLRR_SAI2LPEN BIT(17) |
| 1904 | #define RCC_MP_APB2LPENCLRR_SAI3LPEN BIT(18) |
| 1905 | #define RCC_MP_APB2LPENCLRR_DFSDMLPEN BIT(20) |
| 1906 | #define RCC_MP_APB2LPENCLRR_ADFSDMLPEN BIT(21) |
| 1907 | #define RCC_MP_APB2LPENCLRR_FDCANLPEN BIT(24) |
| 1908 | |
| 1909 | /* RCC_MP_APB3LPENSETR register fields */ |
| 1910 | #define RCC_MP_APB3LPENSETR_LPTIM2LPEN BIT(0) |
| 1911 | #define RCC_MP_APB3LPENSETR_LPTIM3LPEN BIT(1) |
| 1912 | #define RCC_MP_APB3LPENSETR_LPTIM4LPEN BIT(2) |
| 1913 | #define RCC_MP_APB3LPENSETR_LPTIM5LPEN BIT(3) |
| 1914 | #define RCC_MP_APB3LPENSETR_SAI4LPEN BIT(8) |
| 1915 | #define RCC_MP_APB3LPENSETR_SYSCFGLPEN BIT(11) |
| 1916 | #define RCC_MP_APB3LPENSETR_VREFLPEN BIT(13) |
| 1917 | #define RCC_MP_APB3LPENSETR_TMPSENSLPEN BIT(16) |
| 1918 | #define RCC_MP_APB3LPENSETR_PMBCTRLLPEN BIT(17) |
| 1919 | |
| 1920 | /* RCC_MP_APB3LPENCLRR register fields */ |
| 1921 | #define RCC_MP_APB3LPENCLRR_LPTIM2LPEN BIT(0) |
| 1922 | #define RCC_MP_APB3LPENCLRR_LPTIM3LPEN BIT(1) |
| 1923 | #define RCC_MP_APB3LPENCLRR_LPTIM4LPEN BIT(2) |
| 1924 | #define RCC_MP_APB3LPENCLRR_LPTIM5LPEN BIT(3) |
| 1925 | #define RCC_MP_APB3LPENCLRR_SAI4LPEN BIT(8) |
| 1926 | #define RCC_MP_APB3LPENCLRR_SYSCFGLPEN BIT(11) |
| 1927 | #define RCC_MP_APB3LPENCLRR_VREFLPEN BIT(13) |
| 1928 | #define RCC_MP_APB3LPENCLRR_TMPSENSLPEN BIT(16) |
| 1929 | #define RCC_MP_APB3LPENCLRR_PMBCTRLLPEN BIT(17) |
| 1930 | |
| 1931 | /* RCC_MP_AHB2LPENSETR register fields */ |
| 1932 | #define RCC_MP_AHB2LPENSETR_DMA1LPEN BIT(0) |
| 1933 | #define RCC_MP_AHB2LPENSETR_DMA2LPEN BIT(1) |
| 1934 | #define RCC_MP_AHB2LPENSETR_DMAMUXLPEN BIT(2) |
| 1935 | #define RCC_MP_AHB2LPENSETR_ADC12LPEN BIT(5) |
| 1936 | #define RCC_MP_AHB2LPENSETR_USBOLPEN BIT(8) |
| 1937 | #define RCC_MP_AHB2LPENSETR_SDMMC3LPEN BIT(16) |
| 1938 | |
| 1939 | /* RCC_MP_AHB2LPENCLRR register fields */ |
| 1940 | #define RCC_MP_AHB2LPENCLRR_DMA1LPEN BIT(0) |
| 1941 | #define RCC_MP_AHB2LPENCLRR_DMA2LPEN BIT(1) |
| 1942 | #define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN BIT(2) |
| 1943 | #define RCC_MP_AHB2LPENCLRR_ADC12LPEN BIT(5) |
| 1944 | #define RCC_MP_AHB2LPENCLRR_USBOLPEN BIT(8) |
| 1945 | #define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN BIT(16) |
| 1946 | |
| 1947 | /* RCC_MP_AHB3LPENSETR register fields */ |
| 1948 | #define RCC_MP_AHB3LPENSETR_DCMILPEN BIT(0) |
| 1949 | #define RCC_MP_AHB3LPENSETR_CRYP2LPEN BIT(4) |
| 1950 | #define RCC_MP_AHB3LPENSETR_HASH2LPEN BIT(5) |
| 1951 | #define RCC_MP_AHB3LPENSETR_RNG2LPEN BIT(6) |
| 1952 | #define RCC_MP_AHB3LPENSETR_CRC2LPEN BIT(7) |
| 1953 | #define RCC_MP_AHB3LPENSETR_HSEMLPEN BIT(11) |
| 1954 | #define RCC_MP_AHB3LPENSETR_IPCCLPEN BIT(12) |
| 1955 | |
| 1956 | /* RCC_MP_AHB3LPENCLRR register fields */ |
| 1957 | #define RCC_MP_AHB3LPENCLRR_DCMILPEN BIT(0) |
| 1958 | #define RCC_MP_AHB3LPENCLRR_CRYP2LPEN BIT(4) |
| 1959 | #define RCC_MP_AHB3LPENCLRR_HASH2LPEN BIT(5) |
| 1960 | #define RCC_MP_AHB3LPENCLRR_RNG2LPEN BIT(6) |
| 1961 | #define RCC_MP_AHB3LPENCLRR_CRC2LPEN BIT(7) |
| 1962 | #define RCC_MP_AHB3LPENCLRR_HSEMLPEN BIT(11) |
| 1963 | #define RCC_MP_AHB3LPENCLRR_IPCCLPEN BIT(12) |
| 1964 | |
| 1965 | /* RCC_MP_AHB4LPENSETR register fields */ |
| 1966 | #define RCC_MP_AHB4LPENSETR_GPIOALPEN BIT(0) |
| 1967 | #define RCC_MP_AHB4LPENSETR_GPIOBLPEN BIT(1) |
| 1968 | #define RCC_MP_AHB4LPENSETR_GPIOCLPEN BIT(2) |
| 1969 | #define RCC_MP_AHB4LPENSETR_GPIODLPEN BIT(3) |
| 1970 | #define RCC_MP_AHB4LPENSETR_GPIOELPEN BIT(4) |
| 1971 | #define RCC_MP_AHB4LPENSETR_GPIOFLPEN BIT(5) |
| 1972 | #define RCC_MP_AHB4LPENSETR_GPIOGLPEN BIT(6) |
| 1973 | #define RCC_MP_AHB4LPENSETR_GPIOHLPEN BIT(7) |
| 1974 | #define RCC_MP_AHB4LPENSETR_GPIOILPEN BIT(8) |
| 1975 | #define RCC_MP_AHB4LPENSETR_GPIOJLPEN BIT(9) |
| 1976 | #define RCC_MP_AHB4LPENSETR_GPIOKLPEN BIT(10) |
| 1977 | |
| 1978 | /* RCC_MP_AHB4LPENCLRR register fields */ |
| 1979 | #define RCC_MP_AHB4LPENCLRR_GPIOALPEN BIT(0) |
| 1980 | #define RCC_MP_AHB4LPENCLRR_GPIOBLPEN BIT(1) |
| 1981 | #define RCC_MP_AHB4LPENCLRR_GPIOCLPEN BIT(2) |
| 1982 | #define RCC_MP_AHB4LPENCLRR_GPIODLPEN BIT(3) |
| 1983 | #define RCC_MP_AHB4LPENCLRR_GPIOELPEN BIT(4) |
| 1984 | #define RCC_MP_AHB4LPENCLRR_GPIOFLPEN BIT(5) |
| 1985 | #define RCC_MP_AHB4LPENCLRR_GPIOGLPEN BIT(6) |
| 1986 | #define RCC_MP_AHB4LPENCLRR_GPIOHLPEN BIT(7) |
| 1987 | #define RCC_MP_AHB4LPENCLRR_GPIOILPEN BIT(8) |
| 1988 | #define RCC_MP_AHB4LPENCLRR_GPIOJLPEN BIT(9) |
| 1989 | #define RCC_MP_AHB4LPENCLRR_GPIOKLPEN BIT(10) |
| 1990 | |
| 1991 | /* RCC_MP_AXIMLPENSETR register fields */ |
| 1992 | #define RCC_MP_AXIMLPENSETR_SYSRAMLPEN BIT(0) |
| 1993 | |
| 1994 | /* RCC_MP_AXIMLPENCLRR register fields */ |
| 1995 | #define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN BIT(0) |
| 1996 | |
| 1997 | /* RCC_MP_MLAHBLPENSETR register fields */ |
| 1998 | #define RCC_MP_MLAHBLPENSETR_SRAM1LPEN BIT(0) |
| 1999 | #define RCC_MP_MLAHBLPENSETR_SRAM2LPEN BIT(1) |
| 2000 | #define RCC_MP_MLAHBLPENSETR_SRAM34LPEN BIT(2) |
| 2001 | #define RCC_MP_MLAHBLPENSETR_RETRAMLPEN BIT(4) |
| 2002 | |
| 2003 | /* RCC_MP_MLAHBLPENCLRR register fields */ |
| 2004 | #define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN BIT(0) |
| 2005 | #define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN BIT(1) |
| 2006 | #define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN BIT(2) |
| 2007 | #define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN BIT(4) |
| 2008 | |
| 2009 | /* RCC_MC_APB1LPENSETR register fields */ |
| 2010 | #define RCC_MC_APB1LPENSETR_TIM2LPEN BIT(0) |
| 2011 | #define RCC_MC_APB1LPENSETR_TIM3LPEN BIT(1) |
| 2012 | #define RCC_MC_APB1LPENSETR_TIM4LPEN BIT(2) |
| 2013 | #define RCC_MC_APB1LPENSETR_TIM5LPEN BIT(3) |
| 2014 | #define RCC_MC_APB1LPENSETR_TIM6LPEN BIT(4) |
| 2015 | #define RCC_MC_APB1LPENSETR_TIM7LPEN BIT(5) |
| 2016 | #define RCC_MC_APB1LPENSETR_TIM12LPEN BIT(6) |
| 2017 | #define RCC_MC_APB1LPENSETR_TIM13LPEN BIT(7) |
| 2018 | #define RCC_MC_APB1LPENSETR_TIM14LPEN BIT(8) |
| 2019 | #define RCC_MC_APB1LPENSETR_LPTIM1LPEN BIT(9) |
| 2020 | #define RCC_MC_APB1LPENSETR_SPI2LPEN BIT(11) |
| 2021 | #define RCC_MC_APB1LPENSETR_SPI3LPEN BIT(12) |
| 2022 | #define RCC_MC_APB1LPENSETR_USART2LPEN BIT(14) |
| 2023 | #define RCC_MC_APB1LPENSETR_USART3LPEN BIT(15) |
| 2024 | #define RCC_MC_APB1LPENSETR_UART4LPEN BIT(16) |
| 2025 | #define RCC_MC_APB1LPENSETR_UART5LPEN BIT(17) |
| 2026 | #define RCC_MC_APB1LPENSETR_UART7LPEN BIT(18) |
| 2027 | #define RCC_MC_APB1LPENSETR_UART8LPEN BIT(19) |
| 2028 | #define RCC_MC_APB1LPENSETR_I2C1LPEN BIT(21) |
| 2029 | #define RCC_MC_APB1LPENSETR_I2C2LPEN BIT(22) |
| 2030 | #define RCC_MC_APB1LPENSETR_I2C3LPEN BIT(23) |
| 2031 | #define RCC_MC_APB1LPENSETR_I2C5LPEN BIT(24) |
| 2032 | #define RCC_MC_APB1LPENSETR_SPDIFLPEN BIT(26) |
| 2033 | #define RCC_MC_APB1LPENSETR_CECLPEN BIT(27) |
| 2034 | #define RCC_MC_APB1LPENSETR_WWDG1LPEN BIT(28) |
| 2035 | #define RCC_MC_APB1LPENSETR_DAC12LPEN BIT(29) |
| 2036 | #define RCC_MC_APB1LPENSETR_MDIOSLPEN BIT(31) |
| 2037 | |
| 2038 | /* RCC_MC_APB1LPENCLRR register fields */ |
| 2039 | #define RCC_MC_APB1LPENCLRR_TIM2LPEN BIT(0) |
| 2040 | #define RCC_MC_APB1LPENCLRR_TIM3LPEN BIT(1) |
| 2041 | #define RCC_MC_APB1LPENCLRR_TIM4LPEN BIT(2) |
| 2042 | #define RCC_MC_APB1LPENCLRR_TIM5LPEN BIT(3) |
| 2043 | #define RCC_MC_APB1LPENCLRR_TIM6LPEN BIT(4) |
| 2044 | #define RCC_MC_APB1LPENCLRR_TIM7LPEN BIT(5) |
| 2045 | #define RCC_MC_APB1LPENCLRR_TIM12LPEN BIT(6) |
| 2046 | #define RCC_MC_APB1LPENCLRR_TIM13LPEN BIT(7) |
| 2047 | #define RCC_MC_APB1LPENCLRR_TIM14LPEN BIT(8) |
| 2048 | #define RCC_MC_APB1LPENCLRR_LPTIM1LPEN BIT(9) |
| 2049 | #define RCC_MC_APB1LPENCLRR_SPI2LPEN BIT(11) |
| 2050 | #define RCC_MC_APB1LPENCLRR_SPI3LPEN BIT(12) |
| 2051 | #define RCC_MC_APB1LPENCLRR_USART2LPEN BIT(14) |
| 2052 | #define RCC_MC_APB1LPENCLRR_USART3LPEN BIT(15) |
| 2053 | #define RCC_MC_APB1LPENCLRR_UART4LPEN BIT(16) |
| 2054 | #define RCC_MC_APB1LPENCLRR_UART5LPEN BIT(17) |
| 2055 | #define RCC_MC_APB1LPENCLRR_UART7LPEN BIT(18) |
| 2056 | #define RCC_MC_APB1LPENCLRR_UART8LPEN BIT(19) |
| 2057 | #define RCC_MC_APB1LPENCLRR_I2C1LPEN BIT(21) |
| 2058 | #define RCC_MC_APB1LPENCLRR_I2C2LPEN BIT(22) |
| 2059 | #define RCC_MC_APB1LPENCLRR_I2C3LPEN BIT(23) |
| 2060 | #define RCC_MC_APB1LPENCLRR_I2C5LPEN BIT(24) |
| 2061 | #define RCC_MC_APB1LPENCLRR_SPDIFLPEN BIT(26) |
| 2062 | #define RCC_MC_APB1LPENCLRR_CECLPEN BIT(27) |
| 2063 | #define RCC_MC_APB1LPENCLRR_WWDG1LPEN BIT(28) |
| 2064 | #define RCC_MC_APB1LPENCLRR_DAC12LPEN BIT(29) |
| 2065 | #define RCC_MC_APB1LPENCLRR_MDIOSLPEN BIT(31) |
| 2066 | |
| 2067 | /* RCC_MC_APB2LPENSETR register fields */ |
| 2068 | #define RCC_MC_APB2LPENSETR_TIM1LPEN BIT(0) |
| 2069 | #define RCC_MC_APB2LPENSETR_TIM8LPEN BIT(1) |
| 2070 | #define RCC_MC_APB2LPENSETR_TIM15LPEN BIT(2) |
| 2071 | #define RCC_MC_APB2LPENSETR_TIM16LPEN BIT(3) |
| 2072 | #define RCC_MC_APB2LPENSETR_TIM17LPEN BIT(4) |
| 2073 | #define RCC_MC_APB2LPENSETR_SPI1LPEN BIT(8) |
| 2074 | #define RCC_MC_APB2LPENSETR_SPI4LPEN BIT(9) |
| 2075 | #define RCC_MC_APB2LPENSETR_SPI5LPEN BIT(10) |
| 2076 | #define RCC_MC_APB2LPENSETR_USART6LPEN BIT(13) |
| 2077 | #define RCC_MC_APB2LPENSETR_SAI1LPEN BIT(16) |
| 2078 | #define RCC_MC_APB2LPENSETR_SAI2LPEN BIT(17) |
| 2079 | #define RCC_MC_APB2LPENSETR_SAI3LPEN BIT(18) |
| 2080 | #define RCC_MC_APB2LPENSETR_DFSDMLPEN BIT(20) |
| 2081 | #define RCC_MC_APB2LPENSETR_ADFSDMLPEN BIT(21) |
| 2082 | #define RCC_MC_APB2LPENSETR_FDCANLPEN BIT(24) |
| 2083 | |
| 2084 | /* RCC_MC_APB2LPENCLRR register fields */ |
| 2085 | #define RCC_MC_APB2LPENCLRR_TIM1LPEN BIT(0) |
| 2086 | #define RCC_MC_APB2LPENCLRR_TIM8LPEN BIT(1) |
| 2087 | #define RCC_MC_APB2LPENCLRR_TIM15LPEN BIT(2) |
| 2088 | #define RCC_MC_APB2LPENCLRR_TIM16LPEN BIT(3) |
| 2089 | #define RCC_MC_APB2LPENCLRR_TIM17LPEN BIT(4) |
| 2090 | #define RCC_MC_APB2LPENCLRR_SPI1LPEN BIT(8) |
| 2091 | #define RCC_MC_APB2LPENCLRR_SPI4LPEN BIT(9) |
| 2092 | #define RCC_MC_APB2LPENCLRR_SPI5LPEN BIT(10) |
| 2093 | #define RCC_MC_APB2LPENCLRR_USART6LPEN BIT(13) |
| 2094 | #define RCC_MC_APB2LPENCLRR_SAI1LPEN BIT(16) |
| 2095 | #define RCC_MC_APB2LPENCLRR_SAI2LPEN BIT(17) |
| 2096 | #define RCC_MC_APB2LPENCLRR_SAI3LPEN BIT(18) |
| 2097 | #define RCC_MC_APB2LPENCLRR_DFSDMLPEN BIT(20) |
| 2098 | #define RCC_MC_APB2LPENCLRR_ADFSDMLPEN BIT(21) |
| 2099 | #define RCC_MC_APB2LPENCLRR_FDCANLPEN BIT(24) |
| 2100 | |
| 2101 | /* RCC_MC_APB3LPENSETR register fields */ |
| 2102 | #define RCC_MC_APB3LPENSETR_LPTIM2LPEN BIT(0) |
| 2103 | #define RCC_MC_APB3LPENSETR_LPTIM3LPEN BIT(1) |
| 2104 | #define RCC_MC_APB3LPENSETR_LPTIM4LPEN BIT(2) |
| 2105 | #define RCC_MC_APB3LPENSETR_LPTIM5LPEN BIT(3) |
| 2106 | #define RCC_MC_APB3LPENSETR_SAI4LPEN BIT(8) |
| 2107 | #define RCC_MC_APB3LPENSETR_SYSCFGLPEN BIT(11) |
| 2108 | #define RCC_MC_APB3LPENSETR_VREFLPEN BIT(13) |
| 2109 | #define RCC_MC_APB3LPENSETR_TMPSENSLPEN BIT(16) |
| 2110 | #define RCC_MC_APB3LPENSETR_PMBCTRLLPEN BIT(17) |
| 2111 | |
| 2112 | /* RCC_MC_APB3LPENCLRR register fields */ |
| 2113 | #define RCC_MC_APB3LPENCLRR_LPTIM2LPEN BIT(0) |
| 2114 | #define RCC_MC_APB3LPENCLRR_LPTIM3LPEN BIT(1) |
| 2115 | #define RCC_MC_APB3LPENCLRR_LPTIM4LPEN BIT(2) |
| 2116 | #define RCC_MC_APB3LPENCLRR_LPTIM5LPEN BIT(3) |
| 2117 | #define RCC_MC_APB3LPENCLRR_SAI4LPEN BIT(8) |
| 2118 | #define RCC_MC_APB3LPENCLRR_SYSCFGLPEN BIT(11) |
| 2119 | #define RCC_MC_APB3LPENCLRR_VREFLPEN BIT(13) |
| 2120 | #define RCC_MC_APB3LPENCLRR_TMPSENSLPEN BIT(16) |
| 2121 | #define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN BIT(17) |
| 2122 | |
| 2123 | /* RCC_MC_AHB2LPENSETR register fields */ |
| 2124 | #define RCC_MC_AHB2LPENSETR_DMA1LPEN BIT(0) |
| 2125 | #define RCC_MC_AHB2LPENSETR_DMA2LPEN BIT(1) |
| 2126 | #define RCC_MC_AHB2LPENSETR_DMAMUXLPEN BIT(2) |
| 2127 | #define RCC_MC_AHB2LPENSETR_ADC12LPEN BIT(5) |
| 2128 | #define RCC_MC_AHB2LPENSETR_USBOLPEN BIT(8) |
| 2129 | #define RCC_MC_AHB2LPENSETR_SDMMC3LPEN BIT(16) |
| 2130 | |
| 2131 | /* RCC_MC_AHB2LPENCLRR register fields */ |
| 2132 | #define RCC_MC_AHB2LPENCLRR_DMA1LPEN BIT(0) |
| 2133 | #define RCC_MC_AHB2LPENCLRR_DMA2LPEN BIT(1) |
| 2134 | #define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN BIT(2) |
| 2135 | #define RCC_MC_AHB2LPENCLRR_ADC12LPEN BIT(5) |
| 2136 | #define RCC_MC_AHB2LPENCLRR_USBOLPEN BIT(8) |
| 2137 | #define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN BIT(16) |
| 2138 | |
| 2139 | /* RCC_MC_AHB3LPENSETR register fields */ |
| 2140 | #define RCC_MC_AHB3LPENSETR_DCMILPEN BIT(0) |
| 2141 | #define RCC_MC_AHB3LPENSETR_CRYP2LPEN BIT(4) |
| 2142 | #define RCC_MC_AHB3LPENSETR_HASH2LPEN BIT(5) |
| 2143 | #define RCC_MC_AHB3LPENSETR_RNG2LPEN BIT(6) |
| 2144 | #define RCC_MC_AHB3LPENSETR_CRC2LPEN BIT(7) |
| 2145 | #define RCC_MC_AHB3LPENSETR_HSEMLPEN BIT(11) |
| 2146 | #define RCC_MC_AHB3LPENSETR_IPCCLPEN BIT(12) |
| 2147 | |
| 2148 | /* RCC_MC_AHB3LPENCLRR register fields */ |
| 2149 | #define RCC_MC_AHB3LPENCLRR_DCMILPEN BIT(0) |
| 2150 | #define RCC_MC_AHB3LPENCLRR_CRYP2LPEN BIT(4) |
| 2151 | #define RCC_MC_AHB3LPENCLRR_HASH2LPEN BIT(5) |
| 2152 | #define RCC_MC_AHB3LPENCLRR_RNG2LPEN BIT(6) |
| 2153 | #define RCC_MC_AHB3LPENCLRR_CRC2LPEN BIT(7) |
| 2154 | #define RCC_MC_AHB3LPENCLRR_HSEMLPEN BIT(11) |
| 2155 | #define RCC_MC_AHB3LPENCLRR_IPCCLPEN BIT(12) |
| 2156 | |
| 2157 | /* RCC_MC_AHB4LPENSETR register fields */ |
| 2158 | #define RCC_MC_AHB4LPENSETR_GPIOALPEN BIT(0) |
| 2159 | #define RCC_MC_AHB4LPENSETR_GPIOBLPEN BIT(1) |
| 2160 | #define RCC_MC_AHB4LPENSETR_GPIOCLPEN BIT(2) |
| 2161 | #define RCC_MC_AHB4LPENSETR_GPIODLPEN BIT(3) |
| 2162 | #define RCC_MC_AHB4LPENSETR_GPIOELPEN BIT(4) |
| 2163 | #define RCC_MC_AHB4LPENSETR_GPIOFLPEN BIT(5) |
| 2164 | #define RCC_MC_AHB4LPENSETR_GPIOGLPEN BIT(6) |
| 2165 | #define RCC_MC_AHB4LPENSETR_GPIOHLPEN BIT(7) |
| 2166 | #define RCC_MC_AHB4LPENSETR_GPIOILPEN BIT(8) |
| 2167 | #define RCC_MC_AHB4LPENSETR_GPIOJLPEN BIT(9) |
| 2168 | #define RCC_MC_AHB4LPENSETR_GPIOKLPEN BIT(10) |
| 2169 | |
| 2170 | /* RCC_MC_AHB4LPENCLRR register fields */ |
| 2171 | #define RCC_MC_AHB4LPENCLRR_GPIOALPEN BIT(0) |
| 2172 | #define RCC_MC_AHB4LPENCLRR_GPIOBLPEN BIT(1) |
| 2173 | #define RCC_MC_AHB4LPENCLRR_GPIOCLPEN BIT(2) |
| 2174 | #define RCC_MC_AHB4LPENCLRR_GPIODLPEN BIT(3) |
| 2175 | #define RCC_MC_AHB4LPENCLRR_GPIOELPEN BIT(4) |
| 2176 | #define RCC_MC_AHB4LPENCLRR_GPIOFLPEN BIT(5) |
| 2177 | #define RCC_MC_AHB4LPENCLRR_GPIOGLPEN BIT(6) |
| 2178 | #define RCC_MC_AHB4LPENCLRR_GPIOHLPEN BIT(7) |
| 2179 | #define RCC_MC_AHB4LPENCLRR_GPIOILPEN BIT(8) |
| 2180 | #define RCC_MC_AHB4LPENCLRR_GPIOJLPEN BIT(9) |
| 2181 | #define RCC_MC_AHB4LPENCLRR_GPIOKLPEN BIT(10) |
| 2182 | |
| 2183 | /* RCC_MC_AXIMLPENSETR register fields */ |
| 2184 | #define RCC_MC_AXIMLPENSETR_SYSRAMLPEN BIT(0) |
| 2185 | |
| 2186 | /* RCC_MC_AXIMLPENCLRR register fields */ |
| 2187 | #define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN BIT(0) |
| 2188 | |
| 2189 | /* RCC_MC_MLAHBLPENSETR register fields */ |
| 2190 | #define RCC_MC_MLAHBLPENSETR_SRAM1LPEN BIT(0) |
| 2191 | #define RCC_MC_MLAHBLPENSETR_SRAM2LPEN BIT(1) |
| 2192 | #define RCC_MC_MLAHBLPENSETR_SRAM34LPEN BIT(2) |
| 2193 | #define RCC_MC_MLAHBLPENSETR_RETRAMLPEN BIT(4) |
| 2194 | |
| 2195 | /* RCC_MC_MLAHBLPENCLRR register fields */ |
| 2196 | #define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN BIT(0) |
| 2197 | #define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN BIT(1) |
| 2198 | #define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN BIT(2) |
| 2199 | #define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN BIT(4) |
| 2200 | |
| 2201 | /* RCC_MC_RSTSCLRR register fields */ |
| 2202 | #define RCC_MC_RSTSCLRR_PORRSTF BIT(0) |
| 2203 | #define RCC_MC_RSTSCLRR_BORRSTF BIT(1) |
| 2204 | #define RCC_MC_RSTSCLRR_PADRSTF BIT(2) |
| 2205 | #define RCC_MC_RSTSCLRR_HCSSRSTF BIT(3) |
| 2206 | #define RCC_MC_RSTSCLRR_VCORERSTF BIT(4) |
| 2207 | #define RCC_MC_RSTSCLRR_MCURSTF BIT(5) |
| 2208 | #define RCC_MC_RSTSCLRR_MPSYSRSTF BIT(6) |
| 2209 | #define RCC_MC_RSTSCLRR_MCSYSRSTF BIT(7) |
| 2210 | #define RCC_MC_RSTSCLRR_IWDG1RSTF BIT(8) |
| 2211 | #define RCC_MC_RSTSCLRR_IWDG2RSTF BIT(9) |
| 2212 | #define RCC_MC_RSTSCLRR_WWDG1RSTF BIT(10) |
| 2213 | |
| 2214 | /* RCC_MC_CIER register fields */ |
| 2215 | #define RCC_MC_CIER_LSIRDYIE BIT(0) |
| 2216 | #define RCC_MC_CIER_LSERDYIE BIT(1) |
| 2217 | #define RCC_MC_CIER_HSIRDYIE BIT(2) |
| 2218 | #define RCC_MC_CIER_HSERDYIE BIT(3) |
| 2219 | #define RCC_MC_CIER_CSIRDYIE BIT(4) |
| 2220 | #define RCC_MC_CIER_PLL1DYIE BIT(8) |
| 2221 | #define RCC_MC_CIER_PLL2DYIE BIT(9) |
| 2222 | #define RCC_MC_CIER_PLL3DYIE BIT(10) |
| 2223 | #define RCC_MC_CIER_PLL4DYIE BIT(11) |
| 2224 | #define RCC_MC_CIER_LSECSSIE BIT(16) |
| 2225 | #define RCC_MC_CIER_WKUPIE BIT(20) |
| 2226 | |
| 2227 | /* RCC_MC_CIFR register fields */ |
| 2228 | #define RCC_MC_CIFR_LSIRDYF BIT(0) |
| 2229 | #define RCC_MC_CIFR_LSERDYF BIT(1) |
| 2230 | #define RCC_MC_CIFR_HSIRDYF BIT(2) |
| 2231 | #define RCC_MC_CIFR_HSERDYF BIT(3) |
| 2232 | #define RCC_MC_CIFR_CSIRDYF BIT(4) |
| 2233 | #define RCC_MC_CIFR_PLL1DYF BIT(8) |
| 2234 | #define RCC_MC_CIFR_PLL2DYF BIT(9) |
| 2235 | #define RCC_MC_CIFR_PLL3DYF BIT(10) |
| 2236 | #define RCC_MC_CIFR_PLL4DYF BIT(11) |
| 2237 | #define RCC_MC_CIFR_LSECSSF BIT(16) |
| 2238 | #define RCC_MC_CIFR_WKUPF BIT(20) |
| 2239 | |
| 2240 | /* RCC_VERR register fields */ |
| 2241 | #define RCC_VERR_MINREV_MASK GENMASK(3, 0) |
| 2242 | #define RCC_VERR_MINREV_SHIFT 0 |
| 2243 | #define RCC_VERR_MAJREV_MASK GENMASK(7, 4) |
| 2244 | #define RCC_VERR_MAJREV_SHIFT 4 |
| 2245 | |
| 2246 | /* Used for RCC_OCENSETR and RCC_OCENCLRR registers */ |
| 2247 | #define RCC_OCENR_HSION BIT(0) |
| 2248 | #define RCC_OCENR_HSIKERON BIT(1) |
| 2249 | #define RCC_OCENR_CSION BIT(4) |
| 2250 | #define RCC_OCENR_CSIKERON BIT(5) |
| 2251 | #define RCC_OCENR_DIGBYP BIT(7) |
| 2252 | #define RCC_OCENR_HSEON BIT(8) |
| 2253 | #define RCC_OCENR_HSEKERON BIT(9) |
| 2254 | #define RCC_OCENR_HSEBYP BIT(10) |
| 2255 | #define RCC_OCENR_HSECSSON BIT(11) |
| 2256 | |
| 2257 | /* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ |
| 2258 | #define RCC_MP_ENCLRR_OFFSET U(4) |
| 2259 | |
| 2260 | /* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */ |
| 2261 | #define RCC_RSTCLRR_OFFSET U(4) |
| 2262 | |
| 2263 | /* Used for most of DIVR register: max div for RTC */ |
| 2264 | #define RCC_DIVR_DIV_MASK GENMASK(5, 0) |
| 2265 | #define RCC_DIVR_DIVRDY BIT(31) |
| 2266 | |
| 2267 | /* Masks for specific DIVR registers */ |
| 2268 | #define RCC_APBXDIV_MASK GENMASK(2, 0) |
| 2269 | #define RCC_MPUDIV_MASK GENMASK(2, 0) |
| 2270 | #define RCC_AXIDIV_MASK GENMASK(2, 0) |
| 2271 | #define RCC_MCUDIV_MASK GENMASK(3, 0) |
| 2272 | |
| 2273 | /* Used for most of RCC_<x>SELR registers */ |
| 2274 | #define RCC_SELR_SRC_MASK GENMASK(2, 0) |
| 2275 | #define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0) |
| 2276 | #define RCC_SELR_SRCRDY BIT(31) |
| 2277 | |
| 2278 | /* Used for all RCC_PLL<n>CR registers */ |
| 2279 | #define RCC_PLLNCR_PLLON BIT(0) |
| 2280 | #define RCC_PLLNCR_PLLRDY BIT(1) |
| 2281 | #define RCC_PLLNCR_SSCG_CTRL BIT(2) |
| 2282 | #define RCC_PLLNCR_DIVPEN BIT(4) |
| 2283 | #define RCC_PLLNCR_DIVQEN BIT(5) |
| 2284 | #define RCC_PLLNCR_DIVREN BIT(6) |
| 2285 | #define RCC_PLLNCR_DIVEN_SHIFT 4 |
| 2286 | |
| 2287 | /* Used for all RCC_PLL<n>CFGR1 registers */ |
| 2288 | #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) |
| 2289 | #define RCC_PLLNCFGR1_DIVM_SHIFT 16 |
| 2290 | #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) |
| 2291 | #define RCC_PLLNCFGR1_DIVN_SHIFT 0 |
| 2292 | |
| 2293 | /* Only for PLL3 and PLL4 */ |
| 2294 | #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) |
| 2295 | #define RCC_PLLNCFGR1_IFRGE_SHIFT 24 |
| 2296 | |
| 2297 | /* Used for all RCC_PLL<n>CFGR2 registers */ |
| 2298 | #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) |
| 2299 | #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) |
| 2300 | #define RCC_PLLNCFGR2_DIVP_SHIFT 0 |
| 2301 | #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) |
| 2302 | #define RCC_PLLNCFGR2_DIVQ_SHIFT 8 |
| 2303 | #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) |
| 2304 | #define RCC_PLLNCFGR2_DIVR_SHIFT 16 |
| 2305 | |
| 2306 | /* Used for all RCC_PLL<n>FRACR registers */ |
| 2307 | #define RCC_PLLNFRACR_FRACV_SHIFT 3 |
| 2308 | #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) |
| 2309 | #define RCC_PLLNFRACR_FRACLE BIT(16) |
| 2310 | |
| 2311 | /* Used for all RCC_PLL<n>CSGR registers */ |
| 2312 | #define RCC_PLLNCSGR_INC_STEP_SHIFT 16 |
| 2313 | #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) |
| 2314 | #define RCC_PLLNCSGR_MOD_PER_SHIFT 0 |
| 2315 | #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) |
| 2316 | #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 |
| 2317 | #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) |
| 2318 | |
| 2319 | /* Used for TIMER Prescaler */ |
| 2320 | #define RCC_TIMGXPRER_TIMGXPRE BIT(0) |
| 2321 | |
| 2322 | /* Used for RCC_MCO related operations */ |
| 2323 | #define RCC_MCOCFG_MCOON BIT(12) |
| 2324 | #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) |
| 2325 | #define RCC_MCOCFG_MCODIV_SHIFT 4 |
| 2326 | #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) |
| 2327 | |
| 2328 | #endif /* STM32MP1_RCC_H */ |