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git01.mediatek.com / filogic / atf / bfdb726170361316f3a04b416e21850a6a0484f8 / . / plat / arm / board / corstone1000 / common / corstone1000_bl2_mem_params_desc.c
blob: fe521a9fac21fea2fc5a7de5f92798e388be209d [file] [log] [blame]
Abdellatif El Khlifiad9b8e52021-04-21 17:20:43 +0100[diff] [blame]1/*
Vishnu Banavath2b651ea2022-01-19 18:43:12 +0000[diff] [blame]2 * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
Abdellatif El Khlifiad9b8e52021-04-21 17:20:43 +0100[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/desc_image_load.h>
8
9#include <platform_def.h>
10
11/*******************************************************************************
12 * Following descriptor provides BL image/ep information that gets used
13 * by BL2 to load the images and also subset of this information is
14 * passed to next BL image. The image loading sequence is managed by
15 * populating the images in required loading order. The image execution
16 * sequence is managed by populating the `next_handoff_image_id` with
17 * the next executable image id.
18 ******************************************************************************/
19static bl_mem_params_node_t bl2_mem_params_descs[] = {
20
21 /* Fill BL31 related information */
22 {
23 .image_id = BL31_IMAGE_ID,
24
25 SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
26 VERSION_2, entry_point_info_t,
27 SECURE | EXECUTABLE | EP_FIRST_EXE),
28 .ep_info.pc = BL31_BASE,
29 .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
30 DISABLE_ALL_EXCEPTIONS),
31 .ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL,
32 SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
33 VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
34 .image_info.image_base = BL31_BASE,
35 .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
36
37 .next_handoff_image_id = BL32_IMAGE_ID,
38 },
39
40 /* Fill BL32 related information */
41 {
42 .image_id = BL32_IMAGE_ID,
43
44 SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
45 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
46 .ep_info.pc = BL32_BASE,
Vishnu Banavath2b651ea2022-01-19 18:43:12 +0000[diff] [blame]47 .ep_info.args.arg0 = CORSTONE1000_TOS_FW_CONFIG_BASE,
Abdellatif El Khlifiad9b8e52021-04-21 17:20:43 +0100[diff] [blame]48 SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
49 VERSION_2, image_info_t, 0),
50 .image_info.image_base = BL32_BASE,
51 .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
52
53 .next_handoff_image_id = BL33_IMAGE_ID,
54 },
55
56 /* Fill TOS_FW_CONFIG related information */
57 {
58 .image_id = TOS_FW_CONFIG_ID,
Vishnu Banavath2b651ea2022-01-19 18:43:12 +0000[diff] [blame]59 .image_info.image_base = CORSTONE1000_TOS_FW_CONFIG_BASE,
David Vinczebfdb7262022-03-03 14:35:51 +0100[diff] [blame^]60 .image_info.image_max_size = (CORSTONE1000_TOS_FW_CONFIG_LIMIT -
61 CORSTONE1000_TOS_FW_CONFIG_BASE),
Abdellatif El Khlifiad9b8e52021-04-21 17:20:43 +0100[diff] [blame]62 SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
63 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
64 SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
65 VERSION_2, image_info_t, 0),
66 .next_handoff_image_id = INVALID_IMAGE_ID,
67 },
68
69 /* Fill BL33 related information */
70 {
71 .image_id = BL33_IMAGE_ID,
72 SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
73 VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
Arpita S.K639f7b72021-10-13 14:49:26 +0530[diff] [blame]74 .ep_info.pc = BL33_BASE,
Abdellatif El Khlifiad9b8e52021-04-21 17:20:43 +0100[diff] [blame]75
76 SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
77 VERSION_2, image_info_t, 0),
Arpita S.K639f7b72021-10-13 14:49:26 +0530[diff] [blame]78 .image_info.image_base = BL33_BASE,
79 .image_info.image_max_size = BL33_LIMIT - BL33_BASE,
Abdellatif El Khlifiad9b8e52021-04-21 17:20:43 +0100[diff] [blame]80
81 .next_handoff_image_id = INVALID_IMAGE_ID,
82 },
83};
84
85REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)