| Juan Pablo Conde | 16d3108 | 2023-09-19 14:57:29 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2023, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef TRAVIS_H |
| 8 | #define TRAVIS_H |
| 9 | |
| 10 | #define TRAVIS_MIDR U(0x410FD8C0) |
| 11 | |
| 12 | /******************************************************************************* |
| 13 | * CPU Extended Control register specific definitions |
| 14 | ******************************************************************************/ |
| 15 | #define TRAVIS_IMP_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 16 | |
| 17 | /******************************************************************************* |
| 18 | * CPU Power Control register specific definitions |
| 19 | ******************************************************************************/ |
| 20 | #define TRAVIS_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 21 | #define TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) |
| 22 | |
| 23 | /******************************************************************************* |
| 24 | * SME Control registers |
| 25 | ******************************************************************************/ |
| 26 | #define TRAVIS_SVCRSM S0_3_C4_C2_3 |
| 27 | #define TRAVIS_SVCRZA S0_3_C4_C4_3 |
| 28 | |
| 29 | #endif /* TRAVIS_H */ |