| Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__ |
| 8 | #define __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__ |
| 9 | |
| 10 | #define SIZE_K(n) ((n) * 1024) |
| 11 | #define SIZE_M(n) ((n) * 1024 * 1024) |
| 12 | |
| 13 | /* |
| 14 | * The parts of the shared defined registers address with AP and M0, |
| 15 | * let's note and mark the previous defines like this: |
| 16 | */ |
| 17 | #define GIC500_BASE (MMIO_BASE + 0x06E00000) |
| 18 | #define UART0_BASE (MMIO_BASE + 0x07180000) |
| 19 | #define UART1_BASE (MMIO_BASE + 0x07190000) |
| 20 | #define UART2_BASE (MMIO_BASE + 0x071A0000) |
| 21 | #define UART3_BASE (MMIO_BASE + 0x071B0000) |
| 22 | |
| 23 | #define PMU_BASE (MMIO_BASE + 0x07310000) |
| 24 | #define PMUGRF_BASE (MMIO_BASE + 0x07320000) |
| 25 | #define SGRF_BASE (MMIO_BASE + 0x07330000) |
| 26 | #define PMUSRAM_BASE (MMIO_BASE + 0x073B0000) |
| 27 | #define PWM_BASE (MMIO_BASE + 0x07420000) |
| 28 | |
| 29 | #define CIC_BASE (MMIO_BASE + 0x07620000) |
| 30 | #define PD_BUS0_BASE (MMIO_BASE + 0x07650000) |
| 31 | #define DCF_BASE (MMIO_BASE + 0x076A0000) |
| 32 | #define GPIO0_BASE (MMIO_BASE + 0x07720000) |
| 33 | #define GPIO1_BASE (MMIO_BASE + 0x07730000) |
| 34 | #define PMUCRU_BASE (MMIO_BASE + 0x07750000) |
| 35 | #define CRU_BASE (MMIO_BASE + 0x07760000) |
| 36 | #define GRF_BASE (MMIO_BASE + 0x07770000) |
| 37 | #define GPIO2_BASE (MMIO_BASE + 0x07780000) |
| 38 | #define GPIO3_BASE (MMIO_BASE + 0x07788000) |
| 39 | #define GPIO4_BASE (MMIO_BASE + 0x07790000) |
| 40 | #define STIME_BASE (MMIO_BASE + 0x07860000) |
| 41 | #define SRAM_BASE (MMIO_BASE + 0x078C0000) |
| 42 | #define SERVICE_NOC_0_BASE (MMIO_BASE + 0x07A50000) |
| 43 | #define DDRC0_BASE (MMIO_BASE + 0x07A80000) |
| 44 | #define SERVICE_NOC_1_BASE (MMIO_BASE + 0x07A84000) |
| 45 | #define DDRC1_BASE (MMIO_BASE + 0x07A88000) |
| 46 | #define SERVICE_NOC_2_BASE (MMIO_BASE + 0x07A8C000) |
| 47 | #define SERVICE_NOC_3_BASE (MMIO_BASE + 0x07A90000) |
| 48 | #define CCI500_BASE (MMIO_BASE + 0x07B00000) |
| 49 | #define COLD_BOOT_BASE (MMIO_BASE + 0x07FF0000) |
| 50 | |
| 51 | /* Registers size */ |
| 52 | #define GIC500_SIZE SIZE_M(2) |
| 53 | #define UART0_SIZE SIZE_K(64) |
| 54 | #define UART1_SIZE SIZE_K(64) |
| 55 | #define UART2_SIZE SIZE_K(64) |
| 56 | #define UART3_SIZE SIZE_K(64) |
| 57 | #define PMU_SIZE SIZE_K(64) |
| 58 | #define PMUGRF_SIZE SIZE_K(64) |
| 59 | #define SGRF_SIZE SIZE_K(64) |
| 60 | #define PMUSRAM_SIZE SIZE_K(64) |
| 61 | #define PMUSRAM_RSIZE SIZE_K(8) |
| 62 | #define PWM_SIZE SIZE_K(64) |
| 63 | #define CIC_SIZE SIZE_K(4) |
| 64 | #define DCF_SIZE SIZE_K(4) |
| 65 | #define GPIO0_SIZE SIZE_K(64) |
| 66 | #define GPIO1_SIZE SIZE_K(64) |
| 67 | #define PMUCRU_SIZE SIZE_K(64) |
| 68 | #define CRU_SIZE SIZE_K(64) |
| 69 | #define GRF_SIZE SIZE_K(64) |
| 70 | #define GPIO2_SIZE SIZE_K(32) |
| 71 | #define GPIO3_SIZE SIZE_K(32) |
| 72 | #define GPIO4_SIZE SIZE_K(32) |
| 73 | #define STIME_SIZE SIZE_K(64) |
| 74 | #define SRAM_SIZE SIZE_K(192) |
| 75 | #define SERVICE_NOC_0_SIZE SIZE_K(192) |
| 76 | #define DDRC0_SIZE SIZE_K(32) |
| 77 | #define SERVICE_NOC_1_SIZE SIZE_K(16) |
| 78 | #define DDRC1_SIZE SIZE_K(32) |
| 79 | #define SERVICE_NOC_2_SIZE SIZE_K(16) |
| 80 | #define SERVICE_NOC_3_SIZE SIZE_K(448) |
| 81 | #define CCI500_SIZE SIZE_M(1) |
| 82 | #define PD_BUS0_SIZE SIZE_K(448) |
| 83 | |
| 84 | /* DDR Registers address */ |
| 85 | #define CTL_BASE(ch) (DDRC0_BASE + (ch) * 0x8000) |
| 86 | #define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4) |
| 87 | |
| 88 | #define PI_OFFSET 0x800 |
| 89 | #define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET) |
| 90 | #define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4) |
| 91 | |
| 92 | #define PHY_OFFSET 0x2000 |
| 93 | #define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET) |
| 94 | #define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4) |
| 95 | |
| 96 | #define MSCH_BASE(ch) (SERVICE_NOC_1_BASE + (ch) * 0x8000) |
| 97 | |
| 98 | #endif /* __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__ */ |