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Caesar Wanga8456902016-10-27 01:12:34 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Caesar Wanga8456902016-10-27 01:12:34 +08005 */
6
7#ifndef __SOC_ROCKCHIP_RK3399_DFS_H__
8#define __SOC_ROCKCHIP_RK3399_DFS_H__
9
10struct rk3399_sdram_default_config {
11 unsigned char bl;
12 /* 1:auto precharge, 0:never auto precharge */
13 unsigned char ap;
14 /* dram driver strength */
15 unsigned char dramds;
16 /* dram ODT, if odt=0, this parameter invalid */
17 unsigned char dramodt;
18 /* ca ODT, if odt=0, this parameter invalid
19 * only used by LPDDR4
20 */
21 unsigned char caodt;
22 unsigned char burst_ref_cnt;
23 /* zqcs period, unit(s) */
24 unsigned char zqcsi;
25};
26
Caesar Wanga8456902016-10-27 01:12:34 +080027struct drv_odt_lp_config {
Caesar Wanga8456902016-10-27 01:12:34 +080028 uint32_t pd_idle;
29 uint32_t sr_idle;
30 uint32_t sr_mc_gate_idle;
31 uint32_t srpd_lite_idle;
32 uint32_t standby_idle;
Derek Basehoreff461d02016-10-20 20:46:43 -070033 uint32_t odt_en;
Caesar Wanga8456902016-10-27 01:12:34 +080034
35 uint32_t dram_side_drv;
36 uint32_t dram_side_dq_odt;
37 uint32_t dram_side_ca_odt;
Caesar Wanga8456902016-10-27 01:12:34 +080038};
39
Caesar Wanga8456902016-10-27 01:12:34 +080040uint32_t ddr_set_rate(uint32_t hz);
41uint32_t ddr_round_rate(uint32_t hz);
42uint32_t ddr_get_rate(void);
Derek Basehoreff461d02016-10-20 20:46:43 -070043uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2);
44void dram_dfs_init(void);
Derek Basehoree13bc542017-02-24 14:31:36 +080045void ddr_prepare_for_sys_suspend(void);
46void ddr_prepare_for_sys_resume(void);
47
Caesar Wanga8456902016-10-27 01:12:34 +080048#endif