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git01.mediatek.com / filogic / atf / bf9ba735a51d11a4d6a40bb702cd51cf1f9ca5ff / . / plat / arm / board / rdn2 / rdn2_topology.c
blob: 24acc4d8151ccf2980e8ac38b8c00d8cef15448e [file] [log] [blame]
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]1/*
Tony K Nadackal11cc9952022-11-12 23:21:20 +0000[diff] [blame]2 * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved.
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <plat/arm/common/plat_arm.h>
8#include <plat/arm/css/common/css_pm.h>
9
10/******************************************************************************
11 * The power domain tree descriptor.
12 ******************************************************************************/
13const unsigned char rd_n2_pd_tree_desc[] = {
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]14 (PLAT_ARM_CLUSTER_COUNT) * (CSS_SGI_CHIP_COUNT),
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]15 CSS_SGI_MAX_CPUS_PER_CLUSTER,
16 CSS_SGI_MAX_CPUS_PER_CLUSTER,
17 CSS_SGI_MAX_CPUS_PER_CLUSTER,
18 CSS_SGI_MAX_CPUS_PER_CLUSTER,
Tony K Nadackal11cc9952022-11-12 23:21:20 +0000[diff] [blame]19#if (PLAT_ARM_CLUSTER_COUNT > 4 || \
20 (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1))
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]21 CSS_SGI_MAX_CPUS_PER_CLUSTER,
22 CSS_SGI_MAX_CPUS_PER_CLUSTER,
23 CSS_SGI_MAX_CPUS_PER_CLUSTER,
24 CSS_SGI_MAX_CPUS_PER_CLUSTER,
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]25#endif
Tony K Nadackal11cc9952022-11-12 23:21:20 +0000[diff] [blame]26#if (PLAT_ARM_CLUSTER_COUNT > 8 || \
27 (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 2))
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]28 CSS_SGI_MAX_CPUS_PER_CLUSTER,
29 CSS_SGI_MAX_CPUS_PER_CLUSTER,
30 CSS_SGI_MAX_CPUS_PER_CLUSTER,
31 CSS_SGI_MAX_CPUS_PER_CLUSTER,
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]32#endif
Tony K Nadackal11cc9952022-11-12 23:21:20 +0000[diff] [blame]33#if (PLAT_ARM_CLUSTER_COUNT > 8 || \
34 (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 3))
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]35 CSS_SGI_MAX_CPUS_PER_CLUSTER,
36 CSS_SGI_MAX_CPUS_PER_CLUSTER,
37 CSS_SGI_MAX_CPUS_PER_CLUSTER,
38 CSS_SGI_MAX_CPUS_PER_CLUSTER,
Aditya Angadif894b9a2021-03-20 12:15:04 +0530[diff] [blame]39#endif
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]40};
41
42/*******************************************************************************
43 * This function returns the topology tree information.
44 ******************************************************************************/
45const unsigned char *plat_get_power_domain_tree_desc(void)
46{
47 return rd_n2_pd_tree_desc;
48}
49
50/*******************************************************************************
51 * The array mapping platform core position (implemented by plat_my_core_pos())
52 * to the SCMI power domain ID implemented by SCP.
53 ******************************************************************************/
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]54#if (CSS_SGI_PLATFORM_VARIANT == 2)
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]55const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
56 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
57 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
58 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
59 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]60#if (CSS_SGI_CHIP_COUNT > 1)
61 (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
62 (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
63 (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
64 (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
65#endif
66#if (CSS_SGI_CHIP_COUNT > 2)
67 (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)),
68 (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)),
69 (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)),
70 (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)),
71#endif
72#if (CSS_SGI_CHIP_COUNT > 3)
73 (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)),
74 (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)),
75 (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)),
76 (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x3)),
77#endif
78};
79#else
80const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
81 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
82 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
83 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
84 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]85 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
86 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
87 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
88 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
Tony K Nadackal11cc9952022-11-12 23:21:20 +0000[diff] [blame]89#if (PLAT_ARM_CLUSTER_COUNT > 8)
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]90 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
91 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
92 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
93 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
94 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
95 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
96 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
97 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)),
Aditya Angadif894b9a2021-03-20 12:15:04 +0530[diff] [blame]98#endif
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]99};
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]100#endif