Soby Mathew | 748be1d | 2016-05-05 14:10:46 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <arch_helpers.h> |
| 33 | #include <assert.h> |
| 34 | #include <bl_common.h> |
| 35 | #include <context.h> |
| 36 | #include <context_mgmt.h> |
| 37 | #include <platform.h> |
| 38 | #include <platform_def.h> |
| 39 | #include <smcc_helpers.h> |
| 40 | #include <string.h> |
| 41 | |
| 42 | /******************************************************************************* |
| 43 | * Context management library initialisation routine. This library is used by |
| 44 | * runtime services to share pointers to 'cpu_context' structures for the secure |
| 45 | * and non-secure states. Management of the structures and their associated |
| 46 | * memory is not done by the context management library e.g. the PSCI service |
| 47 | * manages the cpu context used for entry from and exit to the non-secure state. |
| 48 | * The Secure payload manages the context(s) corresponding to the secure state. |
| 49 | * It also uses this library to get access to the non-secure |
| 50 | * state cpu context pointers. |
| 51 | ******************************************************************************/ |
| 52 | void cm_init(void) |
| 53 | { |
| 54 | /* |
| 55 | * The context management library has only global data to initialize, but |
| 56 | * that will be done when the BSS is zeroed out |
| 57 | */ |
| 58 | } |
| 59 | |
| 60 | /******************************************************************************* |
| 61 | * The following function initializes the cpu_context 'ctx' for |
| 62 | * first use, and sets the initial entrypoint state as specified by the |
| 63 | * entry_point_info structure. |
| 64 | * |
| 65 | * The security state to initialize is determined by the SECURE attribute |
| 66 | * of the entry_point_info. The function returns a pointer to the initialized |
| 67 | * context and sets this as the next context to return to. |
| 68 | * |
| 69 | * The EE and ST attributes are used to configure the endianness and secure |
| 70 | * timer availability for the new execution context. |
| 71 | * |
| 72 | * To prepare the register state for entry call cm_prepare_el3_exit() and |
| 73 | * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to |
| 74 | * cm_e1_sysreg_context_restore(). |
| 75 | ******************************************************************************/ |
| 76 | static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) |
| 77 | { |
| 78 | unsigned int security_state; |
| 79 | uint32_t scr, sctlr; |
| 80 | regs_t *reg_ctx; |
| 81 | |
| 82 | assert(ctx); |
| 83 | |
| 84 | security_state = GET_SECURITY_STATE(ep->h.attr); |
| 85 | |
| 86 | /* Clear any residual register values from the context */ |
| 87 | memset(ctx, 0, sizeof(*ctx)); |
| 88 | |
Soby Mathew | b4a970a | 2016-08-31 12:34:33 +0100 | [diff] [blame] | 89 | reg_ctx = get_regs_ctx(ctx); |
| 90 | |
Soby Mathew | 748be1d | 2016-05-05 14:10:46 +0100 | [diff] [blame] | 91 | /* |
| 92 | * Base the context SCR on the current value, adjust for entry point |
| 93 | * specific requirements |
| 94 | */ |
| 95 | scr = read_scr(); |
| 96 | scr &= ~(SCR_NS_BIT | SCR_HCE_BIT); |
| 97 | |
| 98 | if (security_state != SECURE) |
| 99 | scr |= SCR_NS_BIT; |
| 100 | |
| 101 | /* |
| 102 | * Set up SCTLR for the Non Secure context. |
| 103 | * EE bit is taken from the entrypoint attributes |
| 104 | * M, C and I bits must be zero (as required by PSCI specification) |
| 105 | * |
| 106 | * The target exception level is based on the spsr mode requested. |
| 107 | * If execution is requested to hyp mode, HVC is enabled |
| 108 | * via SCR.HCE. |
| 109 | * |
| 110 | * Always compute the SCTLR_EL1 value and save in the cpu_context |
| 111 | * - the HYP registers are set up by cm_preapre_ns_entry() as they |
| 112 | * are not part of the stored cpu_context |
| 113 | * |
| 114 | * TODO: In debug builds the spsr should be validated and checked |
| 115 | * against the CPU support, security state, endianness and pc |
| 116 | */ |
| 117 | if (security_state != SECURE) { |
| 118 | sctlr = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0; |
| 119 | sctlr |= SCTLR_RES1; |
| 120 | write_ctx_reg(reg_ctx, CTX_NS_SCTLR, sctlr); |
| 121 | } |
| 122 | |
| 123 | if (GET_M32(ep->spsr) == MODE32_hyp) |
| 124 | scr |= SCR_HCE_BIT; |
| 125 | |
Soby Mathew | 748be1d | 2016-05-05 14:10:46 +0100 | [diff] [blame] | 126 | write_ctx_reg(reg_ctx, CTX_SCR, scr); |
| 127 | write_ctx_reg(reg_ctx, CTX_LR, ep->pc); |
| 128 | write_ctx_reg(reg_ctx, CTX_SPSR, ep->spsr); |
| 129 | |
| 130 | /* |
| 131 | * Store the r0-r3 value from the entrypoint into the context |
| 132 | * Use memcpy as we are in control of the layout of the structures |
| 133 | */ |
| 134 | memcpy((void *)reg_ctx, (void *)&ep->args, sizeof(aapcs32_params_t)); |
| 135 | } |
| 136 | |
| 137 | /******************************************************************************* |
| 138 | * The following function initializes the cpu_context for a CPU specified by |
| 139 | * its `cpu_idx` for first use, and sets the initial entrypoint state as |
| 140 | * specified by the entry_point_info structure. |
| 141 | ******************************************************************************/ |
| 142 | void cm_init_context_by_index(unsigned int cpu_idx, |
| 143 | const entry_point_info_t *ep) |
| 144 | { |
| 145 | cpu_context_t *ctx; |
| 146 | ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); |
| 147 | cm_init_context_common(ctx, ep); |
| 148 | } |
| 149 | |
| 150 | /******************************************************************************* |
| 151 | * The following function initializes the cpu_context for the current CPU |
| 152 | * for first use, and sets the initial entrypoint state as specified by the |
| 153 | * entry_point_info structure. |
| 154 | ******************************************************************************/ |
| 155 | void cm_init_my_context(const entry_point_info_t *ep) |
| 156 | { |
| 157 | cpu_context_t *ctx; |
| 158 | ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); |
| 159 | cm_init_context_common(ctx, ep); |
| 160 | } |
| 161 | |
| 162 | /******************************************************************************* |
| 163 | * Prepare the CPU system registers for first entry into secure or normal world |
| 164 | * |
| 165 | * If execution is requested to hyp mode, HSCTLR is initialized |
| 166 | * If execution is requested to non-secure PL1, and the CPU supports |
| 167 | * HYP mode then HYP mode is disabled by configuring all necessary HYP mode |
| 168 | * registers. |
| 169 | ******************************************************************************/ |
| 170 | void cm_prepare_el3_exit(uint32_t security_state) |
| 171 | { |
| 172 | uint32_t sctlr, scr, hcptr; |
| 173 | cpu_context_t *ctx = cm_get_context(security_state); |
| 174 | |
| 175 | assert(ctx); |
| 176 | |
| 177 | if (security_state == NON_SECURE) { |
| 178 | scr = read_ctx_reg(get_regs_ctx(ctx), CTX_SCR); |
| 179 | if (scr & SCR_HCE_BIT) { |
| 180 | /* Use SCTLR value to initialize HSCTLR */ |
| 181 | sctlr = read_ctx_reg(get_regs_ctx(ctx), |
| 182 | CTX_NS_SCTLR); |
| 183 | sctlr |= HSCTLR_RES1; |
| 184 | /* Temporarily set the NS bit to access HSCTLR */ |
| 185 | write_scr(read_scr() | SCR_NS_BIT); |
| 186 | /* |
| 187 | * Make sure the write to SCR is complete so that |
| 188 | * we can access HSCTLR |
| 189 | */ |
| 190 | isb(); |
| 191 | write_hsctlr(sctlr); |
| 192 | isb(); |
| 193 | |
| 194 | write_scr(read_scr() & ~SCR_NS_BIT); |
| 195 | isb(); |
| 196 | } else if (read_id_pfr1() & |
| 197 | (ID_PFR1_VIRTEXT_MASK << ID_PFR1_VIRTEXT_SHIFT)) { |
| 198 | /* Set the NS bit to access HCR, HCPTR, CNTHCTL, VPIDR, VMPIDR */ |
| 199 | write_scr(read_scr() | SCR_NS_BIT); |
| 200 | isb(); |
| 201 | |
| 202 | /* PL2 present but unused, need to disable safely */ |
| 203 | write_hcr(0); |
| 204 | |
| 205 | /* HSCTLR : can be ignored when bypassing */ |
| 206 | |
| 207 | /* HCPTR : disable all traps TCPAC, TTA, TCP */ |
| 208 | hcptr = read_hcptr(); |
| 209 | hcptr &= ~(TCPAC_BIT | TTA_BIT | TCP11_BIT | TCP10_BIT); |
| 210 | write_hcptr(hcptr); |
| 211 | |
| 212 | /* Enable EL1 access to timer */ |
| 213 | write_cnthctl(PL1PCEN_BIT | PL1PCTEN_BIT); |
| 214 | |
| 215 | /* Reset CNTVOFF_EL2 */ |
| 216 | write64_cntvoff(0); |
| 217 | |
| 218 | /* Set VPIDR, VMPIDR to match MIDR, MPIDR */ |
| 219 | write_vpidr(read_midr()); |
| 220 | write_vmpidr(read_mpidr()); |
| 221 | |
| 222 | /* |
| 223 | * Reset VTTBR. |
| 224 | * Needed because cache maintenance operations depend on |
| 225 | * the VMID even when non-secure EL1&0 stage 2 address |
| 226 | * translation are disabled. |
| 227 | */ |
| 228 | write64_vttbr(0); |
| 229 | isb(); |
| 230 | |
| 231 | write_scr(read_scr() & ~SCR_NS_BIT); |
| 232 | isb(); |
| 233 | } |
| 234 | } |
| 235 | } |