blob: 4203bba28092ffe7d16fc9564d0263c127701947 [file] [log] [blame]
johpow019d134022021-06-16 17:57:28 -05001/*
2 * Copyright (c) 2021, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef GPT_RME_PRIVATE_H
8#define GPT_RME_PRIVATE_H
9
10#include <arch.h>
11#include <lib/gpt_rme/gpt_rme.h>
12#include <lib/utils_def.h>
13
14/******************************************************************************/
15/* GPT descriptor definitions */
16/******************************************************************************/
17
18/* GPT level 0 descriptor bit definitions. */
19#define GPT_L0_TYPE_MASK UL(0xF)
20#define GPT_L0_TYPE_SHIFT U(0)
21
22/* For now, we don't support contiguous descriptors, only table and block. */
23#define GPT_L0_TYPE_TBL_DESC UL(0x3)
24#define GPT_L0_TYPE_BLK_DESC UL(0x1)
25
26#define GPT_L0_TBL_DESC_L1ADDR_MASK UL(0xFFFFFFFFFF)
27#define GPT_L0_TBL_DESC_L1ADDR_SHIFT U(12)
28
29#define GPT_L0_BLK_DESC_GPI_MASK UL(0xF)
30#define GPT_L0_BLK_DESC_GPI_SHIFT U(4)
31
32/* GPT level 1 descriptor bit definitions */
33#define GPT_L1_GRAN_DESC_GPI_MASK UL(0xF)
34
35/*
36 * This macro fills out every GPI entry in a granules descriptor to the same
37 * value.
38 */
39#define GPT_BUILD_L1_DESC(_gpi) (((uint64_t)(_gpi) << 4*0) | \
40 ((uint64_t)(_gpi) << 4*1) | \
41 ((uint64_t)(_gpi) << 4*2) | \
42 ((uint64_t)(_gpi) << 4*3) | \
43 ((uint64_t)(_gpi) << 4*4) | \
44 ((uint64_t)(_gpi) << 4*5) | \
45 ((uint64_t)(_gpi) << 4*6) | \
46 ((uint64_t)(_gpi) << 4*7) | \
47 ((uint64_t)(_gpi) << 4*8) | \
48 ((uint64_t)(_gpi) << 4*9) | \
49 ((uint64_t)(_gpi) << 4*10) | \
50 ((uint64_t)(_gpi) << 4*11) | \
51 ((uint64_t)(_gpi) << 4*12) | \
52 ((uint64_t)(_gpi) << 4*13) | \
53 ((uint64_t)(_gpi) << 4*14) | \
54 ((uint64_t)(_gpi) << 4*15))
55
56/******************************************************************************/
57/* GPT platform configuration */
58/******************************************************************************/
59
60/* This value comes from GPCCR_EL3 so no externally supplied definition. */
61#define GPT_L0GPTSZ ((unsigned int)((read_gpccr_el3() >> \
62 GPCCR_L0GPTSZ_SHIFT) & GPCCR_L0GPTSZ_MASK))
63
64/* The "S" value is directly related to L0GPTSZ */
65#define GPT_S_VAL (GPT_L0GPTSZ + 30U)
66
67/*
68 * Map PPS values to T values.
69 *
70 * PPS Size T
71 * 0b000 4GB 32
72 * 0b001 64GB 36
73 * 0b010 1TB 40
74 * 0b011 4TB 42
75 * 0b100 16TB 44
76 * 0b101 256TB 48
77 * 0b110 4PB 52
78 *
79 * See section 15.1.27 of the RME specification.
80 */
81typedef enum {
82 PPS_4GB_T = 32U,
83 PPS_64GB_T = 36U,
84 PPS_1TB_T = 40U,
85 PPS_4TB_T = 42U,
86 PPS_16TB_T = 44U,
87 PPS_256TB_T = 48U,
88 PPS_4PB_T = 52U
89} gpt_t_val_e;
90
91/*
92 * Map PGS values to P values.
93 *
94 * PGS Size P
95 * 0b00 4KB 12
96 * 0b10 16KB 14
97 * 0b01 64KB 16
98 *
99 * Note that pgs=0b10 is 16KB and pgs=0b01 is 64KB, this is not a typo.
100 *
101 * See section 15.1.27 of the RME specification.
102 */
103typedef enum {
104 PGS_4KB_P = 12U,
105 PGS_16KB_P = 14U,
106 PGS_64KB_P = 16U
107} gpt_p_val_e;
108
109/* Max valid value for PGS. */
110#define GPT_PGS_MAX (2U)
111
112/* Max valid value for PPS. */
113#define GPT_PPS_MAX (6U)
114
115/******************************************************************************/
116/* L0 address attribute macros */
117/******************************************************************************/
118
119/*
johpow01b984bc42021-10-13 13:56:51 -0500120 * Width of the L0 index field.
121 *
johpow019d134022021-06-16 17:57:28 -0500122 * If S is greater than or equal to T then there is a single L0 region covering
123 * the entire protected space so there is no L0 index, so the width (and the
124 * derivative mask value) are both zero. If we don't specifically handle this
125 * special case we'll get a negative width value which does not make sense and
johpow01b984bc42021-10-13 13:56:51 -0500126 * would cause problems.
johpow019d134022021-06-16 17:57:28 -0500127 */
128#define GPT_L0_IDX_WIDTH(_t) (((_t) > GPT_S_VAL) ? \
129 ((_t) - GPT_S_VAL) : (0U))
130
131/* Bit shift for the L0 index field in a PA. */
132#define GPT_L0_IDX_SHIFT (GPT_S_VAL)
133
johpow01b984bc42021-10-13 13:56:51 -0500134/*
135 * Mask for the L0 index field, must be shifted.
136 *
137 * The value 0x3FFFFF is 22 bits wide which is the maximum possible width of the
138 * L0 index within a physical address. This is calculated by
139 * ((t_max - 1) - s_min + 1) where t_max is 52 for 4PB, the largest PPS, and
140 * s_min is 30 for 1GB, the smallest L0GPTSZ.
141 */
142#define GPT_L0_IDX_MASK(_t) (0x3FFFFFUL >> (22U - \
143 (GPT_L0_IDX_WIDTH(_t))))
johpow019d134022021-06-16 17:57:28 -0500144
145/* Total number of L0 regions. */
146#define GPT_L0_REGION_COUNT(_t) ((GPT_L0_IDX_MASK(_t)) + 1U)
147
148/* Total size of each GPT L0 region in bytes. */
149#define GPT_L0_REGION_SIZE (1UL << (GPT_L0_IDX_SHIFT))
150
151/* Total size in bytes of the whole L0 table. */
152#define GPT_L0_TABLE_SIZE(_t) ((GPT_L0_REGION_COUNT(_t)) << 3U)
153
154/******************************************************************************/
155/* L1 address attribute macros */
156/******************************************************************************/
157
johpow01b984bc42021-10-13 13:56:51 -0500158/*
159 * Width of the L1 index field.
160 *
161 * This field does not have a special case to handle widths less than zero like
162 * the L0 index field above since all valid combinations of PGS (p) and L0GPTSZ
163 * (s) will result in a positive width value.
164 */
johpow019d134022021-06-16 17:57:28 -0500165#define GPT_L1_IDX_WIDTH(_p) ((GPT_S_VAL - 1U) - ((_p) + 3U))
166
167/* Bit shift for the L1 index field. */
168#define GPT_L1_IDX_SHIFT(_p) ((_p) + 4U)
169
johpow01b984bc42021-10-13 13:56:51 -0500170/*
171 * Mask for the L1 index field, must be shifted.
172 *
173 * The value 0x7FFFFF is 23 bits wide and is the maximum possible width of the
174 * L1 index within a physical address. It is calculated by
175 * ((s_max - 1) - (p_min + 4) + 1) where s_max is 39 for 512gb, the largest
176 * L0GPTSZ, and p_min is 12 for 4KB granules, the smallest PGS.
177 */
178#define GPT_L1_IDX_MASK(_p) (0x7FFFFFUL >> (23U - \
179 (GPT_L1_IDX_WIDTH(_p))))
johpow019d134022021-06-16 17:57:28 -0500180
181/* Bit shift for the index of the L1 GPI in a PA. */
182#define GPT_L1_GPI_IDX_SHIFT(_p) (_p)
183
184/* Mask for the index of the L1 GPI in a PA. */
185#define GPT_L1_GPI_IDX_MASK (0xF)
186
187/* Total number of entries in each L1 table. */
188#define GPT_L1_ENTRY_COUNT(_p) ((GPT_L1_IDX_MASK(_p)) + 1U)
189
190/* Total size in bytes of each L1 table. */
191#define GPT_L1_TABLE_SIZE(_p) ((GPT_L1_ENTRY_COUNT(_p)) << 3U)
192
193/******************************************************************************/
194/* General helper macros */
195/******************************************************************************/
196
197/* Protected space actual size in bytes. */
198#define GPT_PPS_ACTUAL_SIZE(_t) (1UL << (_t))
199
200/* Granule actual size in bytes. */
201#define GPT_PGS_ACTUAL_SIZE(_p) (1UL << (_p))
202
203/* L0 GPT region size in bytes. */
204#define GPT_L0GPTSZ_ACTUAL_SIZE (1UL << GPT_S_VAL)
205
206/* Get the index of the L0 entry from a physical address. */
207#define GPT_L0_IDX(_pa) ((_pa) >> GPT_L0_IDX_SHIFT)
208
209/*
210 * This definition is used to determine if a physical address lies on an L0
211 * region boundary.
212 */
213#define GPT_IS_L0_ALIGNED(_pa) (((_pa) & (GPT_L0_REGION_SIZE - U(1))) == U(0))
214
215/* Get the type field from an L0 descriptor. */
216#define GPT_L0_TYPE(_desc) (((_desc) >> GPT_L0_TYPE_SHIFT) & \
217 GPT_L0_TYPE_MASK)
218
219/* Create an L0 block descriptor. */
220#define GPT_L0_BLK_DESC(_gpi) (GPT_L0_TYPE_BLK_DESC | \
221 (((_gpi) & GPT_L0_BLK_DESC_GPI_MASK) << \
222 GPT_L0_BLK_DESC_GPI_SHIFT))
223
224/* Create an L0 table descriptor with an L1 table address. */
225#define GPT_L0_TBL_DESC(_pa) (GPT_L0_TYPE_TBL_DESC | ((uint64_t)(_pa) & \
226 (GPT_L0_TBL_DESC_L1ADDR_MASK << \
227 GPT_L0_TBL_DESC_L1ADDR_SHIFT)))
228
229/* Get the GPI from an L0 block descriptor. */
230#define GPT_L0_BLKD_GPI(_desc) (((_desc) >> GPT_L0_BLK_DESC_GPI_SHIFT) & \
231 GPT_L0_BLK_DESC_GPI_MASK)
232
233/* Get the L1 address from an L0 table descriptor. */
234#define GPT_L0_TBLD_ADDR(_desc) ((uint64_t *)(((_desc) & \
235 (GPT_L0_TBL_DESC_L1ADDR_MASK << \
236 GPT_L0_TBL_DESC_L1ADDR_SHIFT))))
237
238/* Get the index into the L1 table from a physical address. */
239#define GPT_L1_IDX(_p, _pa) (((_pa) >> GPT_L1_IDX_SHIFT(_p)) & \
240 GPT_L1_IDX_MASK(_p))
241
242/* Get the index of the GPI within an L1 table entry from a physical address. */
243#define GPT_L1_GPI_IDX(_p, _pa) (((_pa) >> GPT_L1_GPI_IDX_SHIFT(_p)) & \
244 GPT_L1_GPI_IDX_MASK)
245
246/* Determine if an address is granule-aligned. */
247#define GPT_IS_L1_ALIGNED(_p, _pa) (((_pa) & (GPT_PGS_ACTUAL_SIZE(_p) - U(1))) \
248 == U(0))
249
250#endif /* GPT_RME_PRIVATE_H */