blob: b10da76799268dca5fc4d90bad8e6fdb48206668 [file] [log] [blame]
Varun Wadekarc1d2a282016-11-08 15:46:48 -08001/*
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekarc1d2a282016-11-08 15:46:48 -08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarc1d2a282016-11-08 15:46:48 -08005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
Ambroise Vincentffbf32a2019-03-28 09:01:18 +00008#include <lib/xlat_tables/xlat_tables_v2.h>
Arve Hjønnevågddeb2e72018-02-28 17:15:06 -08009#include <stdbool.h>
Varun Wadekarc1d2a282016-11-08 15:46:48 -080010#include <string.h>
11
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <arch_helpers.h>
13#include <bl31/bl31.h>
14#include <bl31/interrupt_mgmt.h>
15#include <common/bl_common.h>
16#include <common/debug.h>
17#include <common/runtime_svc.h>
18#include <lib/el3_runtime/context_mgmt.h>
19#include <plat/common/platform.h>
20
Varun Wadekarc1d2a282016-11-08 15:46:48 -080021#include "sm_err.h"
Isla Mitchell99305012017-07-11 14:54:08 +010022#include "smcall.h"
Varun Wadekarc1d2a282016-11-08 15:46:48 -080023
Anthony Zhou700ebe52015-10-31 06:03:41 +080024/* macro to check if Hypervisor is enabled in the HCR_EL2 register */
Anthony Zhou50b328a2017-09-19 16:36:22 +080025#define HYP_ENABLE_FLAG 0x286001U
26
27/* length of Trusty's input parameters (in bytes) */
28#define TRUSTY_PARAMS_LEN_BYTES (4096U * 2)
Anthony Zhou700ebe52015-10-31 06:03:41 +080029
Varun Wadekarc1d2a282016-11-08 15:46:48 -080030struct trusty_stack {
31 uint8_t space[PLATFORM_STACK_SIZE] __aligned(16);
Varun Wadekarbd3c9532017-02-16 18:14:37 -080032 uint32_t end;
Varun Wadekarc1d2a282016-11-08 15:46:48 -080033};
34
35struct trusty_cpu_ctx {
36 cpu_context_t cpu_ctx;
37 void *saved_sp;
38 uint32_t saved_security_state;
Anthony Zhou50b328a2017-09-19 16:36:22 +080039 int32_t fiq_handler_active;
Varun Wadekarc1d2a282016-11-08 15:46:48 -080040 uint64_t fiq_handler_pc;
41 uint64_t fiq_handler_cpsr;
42 uint64_t fiq_handler_sp;
43 uint64_t fiq_pc;
44 uint64_t fiq_cpsr;
45 uint64_t fiq_sp_el1;
46 gp_regs_t fiq_gpregs;
47 struct trusty_stack secure_stack;
48};
49
Anthony Zhou50b328a2017-09-19 16:36:22 +080050struct smc_args {
Varun Wadekarc1d2a282016-11-08 15:46:48 -080051 uint64_t r0;
52 uint64_t r1;
53 uint64_t r2;
54 uint64_t r3;
Anthony Zhou700ebe52015-10-31 06:03:41 +080055 uint64_t r4;
56 uint64_t r5;
57 uint64_t r6;
58 uint64_t r7;
Varun Wadekarc1d2a282016-11-08 15:46:48 -080059};
60
Masahiro Yamada56212752018-04-19 01:14:42 +090061static struct trusty_cpu_ctx trusty_cpu_ctx[PLATFORM_CORE_COUNT];
Varun Wadekarc1d2a282016-11-08 15:46:48 -080062
Anthony Zhou50b328a2017-09-19 16:36:22 +080063struct smc_args trusty_init_context_stack(void **sp, void *new_stack);
64struct smc_args trusty_context_switch_helper(void **sp, void *smc_params);
Varun Wadekarc1d2a282016-11-08 15:46:48 -080065
Anthony Zhou43384822016-04-20 10:16:48 +080066static uint32_t current_vmid;
67
Varun Wadekarc1d2a282016-11-08 15:46:48 -080068static struct trusty_cpu_ctx *get_trusty_ctx(void)
69{
70 return &trusty_cpu_ctx[plat_my_core_pos()];
71}
72
Anthony Zhou50b328a2017-09-19 16:36:22 +080073static bool is_hypervisor_mode(void)
Anthony Zhou700ebe52015-10-31 06:03:41 +080074{
75 uint64_t hcr = read_hcr();
76
Anthony Zhou50b328a2017-09-19 16:36:22 +080077 return ((hcr & HYP_ENABLE_FLAG) != 0U) ? true : false;
Anthony Zhou700ebe52015-10-31 06:03:41 +080078}
79
Anthony Zhou50b328a2017-09-19 16:36:22 +080080static struct smc_args trusty_context_switch(uint32_t security_state, uint64_t r0,
Varun Wadekarc1d2a282016-11-08 15:46:48 -080081 uint64_t r1, uint64_t r2, uint64_t r3)
82{
Anthony Zhou50b328a2017-09-19 16:36:22 +080083 struct smc_args args, ret_args;
Varun Wadekarc1d2a282016-11-08 15:46:48 -080084 struct trusty_cpu_ctx *ctx = get_trusty_ctx();
Anthony Zhou700ebe52015-10-31 06:03:41 +080085 struct trusty_cpu_ctx *ctx_smc;
Varun Wadekarc1d2a282016-11-08 15:46:48 -080086
87 assert(ctx->saved_security_state != security_state);
88
Anthony Zhou50b328a2017-09-19 16:36:22 +080089 args.r7 = 0;
Anthony Zhou700ebe52015-10-31 06:03:41 +080090 if (is_hypervisor_mode()) {
91 /* According to the ARM DEN0028A spec, VMID is stored in x7 */
92 ctx_smc = cm_get_context(NON_SECURE);
Anthony Zhou50b328a2017-09-19 16:36:22 +080093 assert(ctx_smc != NULL);
94 args.r7 = SMC_GET_GP(ctx_smc, CTX_GPREG_X7);
Anthony Zhou700ebe52015-10-31 06:03:41 +080095 }
96 /* r4, r5, r6 reserved for future use. */
Anthony Zhou50b328a2017-09-19 16:36:22 +080097 args.r6 = 0;
98 args.r5 = 0;
99 args.r4 = 0;
100 args.r3 = r3;
101 args.r2 = r2;
102 args.r1 = r1;
103 args.r0 = r0;
Anthony Zhou700ebe52015-10-31 06:03:41 +0800104
Aijun Sun98f80902017-09-19 16:52:08 +0800105 /*
106 * To avoid the additional overhead in PSCI flow, skip FP context
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000107 * saving/restoring in case of CPU suspend and resume, assuming that
Aijun Sun98f80902017-09-19 16:52:08 +0800108 * when it's needed the PSCI caller has preserved FP context before
109 * going here.
110 */
Aijun Sun98f80902017-09-19 16:52:08 +0800111 if (r0 != SMC_FC_CPU_SUSPEND && r0 != SMC_FC_CPU_RESUME)
112 fpregs_context_save(get_fpregs_ctx(cm_get_context(security_state)));
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800113 cm_el1_sysregs_context_save(security_state);
114
115 ctx->saved_security_state = security_state;
Anthony Zhou50b328a2017-09-19 16:36:22 +0800116 ret_args = trusty_context_switch_helper(&ctx->saved_sp, &args);
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800117
Anthony Zhou50b328a2017-09-19 16:36:22 +0800118 assert(ctx->saved_security_state == ((security_state == 0U) ? 1U : 0U));
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800119
120 cm_el1_sysregs_context_restore(security_state);
Aijun Sun98f80902017-09-19 16:52:08 +0800121 if (r0 != SMC_FC_CPU_SUSPEND && r0 != SMC_FC_CPU_RESUME)
122 fpregs_context_restore(get_fpregs_ctx(cm_get_context(security_state)));
Aijun Sun98f80902017-09-19 16:52:08 +0800123
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800124 cm_set_next_eret_context(security_state);
125
Anthony Zhou50b328a2017-09-19 16:36:22 +0800126 return ret_args;
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800127}
128
129static uint64_t trusty_fiq_handler(uint32_t id,
130 uint32_t flags,
131 void *handle,
132 void *cookie)
133{
Anthony Zhou50b328a2017-09-19 16:36:22 +0800134 struct smc_args ret;
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800135 struct trusty_cpu_ctx *ctx = get_trusty_ctx();
136
137 assert(!is_caller_secure(flags));
138
139 ret = trusty_context_switch(NON_SECURE, SMC_FC_FIQ_ENTER, 0, 0, 0);
Anthony Zhou50b328a2017-09-19 16:36:22 +0800140 if (ret.r0 != 0U) {
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800141 SMC_RET0(handle);
142 }
143
Anthony Zhou50b328a2017-09-19 16:36:22 +0800144 if (ctx->fiq_handler_active != 0) {
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800145 INFO("%s: fiq handler already active\n", __func__);
146 SMC_RET0(handle);
147 }
148
149 ctx->fiq_handler_active = 1;
Anthony Zhou50b328a2017-09-19 16:36:22 +0800150 (void)memcpy(&ctx->fiq_gpregs, get_gpregs_ctx(handle), sizeof(ctx->fiq_gpregs));
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800151 ctx->fiq_pc = SMC_GET_EL3(handle, CTX_ELR_EL3);
152 ctx->fiq_cpsr = SMC_GET_EL3(handle, CTX_SPSR_EL3);
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000153 ctx->fiq_sp_el1 = read_ctx_reg(get_el1_sysregs_ctx(handle), CTX_SP_EL1);
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800154
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000155 write_ctx_reg(get_el1_sysregs_ctx(handle), CTX_SP_EL1, ctx->fiq_handler_sp);
Anthony Zhou50b328a2017-09-19 16:36:22 +0800156 cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_handler_pc, (uint32_t)ctx->fiq_handler_cpsr);
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800157
158 SMC_RET0(handle);
159}
160
161static uint64_t trusty_set_fiq_handler(void *handle, uint64_t cpu,
162 uint64_t handler, uint64_t stack)
163{
164 struct trusty_cpu_ctx *ctx;
165
Anthony Zhou50b328a2017-09-19 16:36:22 +0800166 if (cpu >= (uint64_t)PLATFORM_CORE_COUNT) {
Masahiro Yamadae93a0f42018-02-02 15:09:36 +0900167 ERROR("%s: cpu %lld >= %d\n", __func__, cpu, PLATFORM_CORE_COUNT);
Anthony Zhou50b328a2017-09-19 16:36:22 +0800168 return (uint64_t)SM_ERR_INVALID_PARAMETERS;
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800169 }
170
171 ctx = &trusty_cpu_ctx[cpu];
172 ctx->fiq_handler_pc = handler;
173 ctx->fiq_handler_cpsr = SMC_GET_EL3(handle, CTX_SPSR_EL3);
174 ctx->fiq_handler_sp = stack;
175
176 SMC_RET1(handle, 0);
177}
178
179static uint64_t trusty_get_fiq_regs(void *handle)
180{
181 struct trusty_cpu_ctx *ctx = get_trusty_ctx();
182 uint64_t sp_el0 = read_ctx_reg(&ctx->fiq_gpregs, CTX_GPREG_SP_EL0);
183
184 SMC_RET4(handle, ctx->fiq_pc, ctx->fiq_cpsr, sp_el0, ctx->fiq_sp_el1);
185}
186
187static uint64_t trusty_fiq_exit(void *handle, uint64_t x1, uint64_t x2, uint64_t x3)
188{
Anthony Zhou50b328a2017-09-19 16:36:22 +0800189 struct smc_args ret;
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800190 struct trusty_cpu_ctx *ctx = get_trusty_ctx();
191
Anthony Zhou50b328a2017-09-19 16:36:22 +0800192 if (ctx->fiq_handler_active == 0) {
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800193 NOTICE("%s: fiq handler not active\n", __func__);
Anthony Zhou50b328a2017-09-19 16:36:22 +0800194 SMC_RET1(handle, (uint64_t)SM_ERR_INVALID_PARAMETERS);
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800195 }
196
197 ret = trusty_context_switch(NON_SECURE, SMC_FC_FIQ_EXIT, 0, 0, 0);
Anthony Zhou50b328a2017-09-19 16:36:22 +0800198 if (ret.r0 != 1U) {
Masahiro Yamadae93a0f42018-02-02 15:09:36 +0900199 INFO("%s(%p) SMC_FC_FIQ_EXIT returned unexpected value, %lld\n",
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800200 __func__, handle, ret.r0);
201 }
202
203 /*
204 * Restore register state to state recorded on fiq entry.
205 *
206 * x0, sp_el1, pc and cpsr need to be restored because el1 cannot
207 * restore them.
208 *
209 * x1-x4 and x8-x17 need to be restored here because smc_handler64
210 * corrupts them (el1 code also restored them).
211 */
Anthony Zhou50b328a2017-09-19 16:36:22 +0800212 (void)memcpy(get_gpregs_ctx(handle), &ctx->fiq_gpregs, sizeof(ctx->fiq_gpregs));
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800213 ctx->fiq_handler_active = 0;
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000214 write_ctx_reg(get_el1_sysregs_ctx(handle), CTX_SP_EL1, ctx->fiq_sp_el1);
Anthony Zhou50b328a2017-09-19 16:36:22 +0800215 cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_pc, (uint32_t)ctx->fiq_cpsr);
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800216
217 SMC_RET0(handle);
218}
219
Masahiro Yamada5ac9d962018-04-19 01:18:48 +0900220static uintptr_t trusty_smc_handler(uint32_t smc_fid,
221 u_register_t x1,
222 u_register_t x2,
223 u_register_t x3,
224 u_register_t x4,
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800225 void *cookie,
226 void *handle,
Masahiro Yamada5ac9d962018-04-19 01:18:48 +0900227 u_register_t flags)
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800228{
Anthony Zhou50b328a2017-09-19 16:36:22 +0800229 struct smc_args ret;
230 uint32_t vmid = 0U;
Varun Wadekar528a7922016-09-29 16:08:16 -0700231 entry_point_info_t *ep_info = bl31_plat_get_next_image_ep_info(SECURE);
232
233 /*
234 * Return success for SET_ROT_PARAMS if Trusty is not present, as
235 * Verified Boot is not even supported and returning success here
236 * would not compromise the boot process.
237 */
Anthony Zhou50b328a2017-09-19 16:36:22 +0800238 if ((ep_info == NULL) && (smc_fid == SMC_YC_SET_ROT_PARAMS)) {
Varun Wadekar528a7922016-09-29 16:08:16 -0700239 SMC_RET1(handle, 0);
Anthony Zhou50b328a2017-09-19 16:36:22 +0800240 } else if (ep_info == NULL) {
Varun Wadekar528a7922016-09-29 16:08:16 -0700241 SMC_RET1(handle, SMC_UNK);
Anthony Zhou50b328a2017-09-19 16:36:22 +0800242 } else {
243 ; /* do nothing */
Varun Wadekar528a7922016-09-29 16:08:16 -0700244 }
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800245
246 if (is_caller_secure(flags)) {
David Cunadoc8833ea2017-04-16 17:15:08 +0100247 if (smc_fid == SMC_YC_NS_RETURN) {
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800248 ret = trusty_context_switch(SECURE, x1, 0, 0, 0);
Anthony Zhou700ebe52015-10-31 06:03:41 +0800249 SMC_RET8(handle, ret.r0, ret.r1, ret.r2, ret.r3,
250 ret.r4, ret.r5, ret.r6, ret.r7);
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800251 }
252 INFO("%s (0x%x, 0x%lx, 0x%lx, 0x%lx, 0x%lx, %p, %p, 0x%lx) \
253 cpu %d, unknown smc\n",
254 __func__, smc_fid, x1, x2, x3, x4, cookie, handle, flags,
255 plat_my_core_pos());
256 SMC_RET1(handle, SMC_UNK);
257 } else {
258 switch (smc_fid) {
259 case SMC_FC64_SET_FIQ_HANDLER:
260 return trusty_set_fiq_handler(handle, x1, x2, x3);
261 case SMC_FC64_GET_FIQ_REGS:
262 return trusty_get_fiq_regs(handle);
263 case SMC_FC_FIQ_EXIT:
264 return trusty_fiq_exit(handle, x1, x2, x3);
265 default:
Anthony Zhou43384822016-04-20 10:16:48 +0800266 if (is_hypervisor_mode())
267 vmid = SMC_GET_GP(handle, CTX_GPREG_X7);
268
269 if ((current_vmid != 0) && (current_vmid != vmid)) {
270 /* This message will cause SMC mechanism
271 * abnormal in multi-guest environment.
272 * Change it to WARN in case you need it.
273 */
274 VERBOSE("Previous SMC not finished.\n");
275 SMC_RET1(handle, SM_ERR_BUSY);
276 }
277 current_vmid = vmid;
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800278 ret = trusty_context_switch(NON_SECURE, smc_fid, x1,
279 x2, x3);
Anthony Zhou43384822016-04-20 10:16:48 +0800280 current_vmid = 0;
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800281 SMC_RET1(handle, ret.r0);
282 }
283 }
284}
285
286static int32_t trusty_init(void)
287{
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800288 entry_point_info_t *ep_info;
Anthony Zhou50b328a2017-09-19 16:36:22 +0800289 struct smc_args zero_args = {0};
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800290 struct trusty_cpu_ctx *ctx = get_trusty_ctx();
291 uint32_t cpu = plat_my_core_pos();
Anthony Zhou50b328a2017-09-19 16:36:22 +0800292 uint64_t reg_width = GET_RW(read_ctx_reg(get_el3state_ctx(&ctx->cpu_ctx),
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800293 CTX_SPSR_EL3));
294
Sandrine Bailleuxf8220902016-11-30 11:24:01 +0000295 /*
296 * Get information about the Trusty image. Its absence is a critical
297 * failure.
298 */
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800299 ep_info = bl31_plat_get_next_image_ep_info(SECURE);
Anthony Zhou50b328a2017-09-19 16:36:22 +0800300 assert(ep_info != NULL);
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800301
Arve Hjønnevågcef22ea2015-08-04 16:19:27 -0700302 fpregs_context_save(get_fpregs_ctx(cm_get_context(NON_SECURE)));
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800303 cm_el1_sysregs_context_save(NON_SECURE);
304
305 cm_set_context(&ctx->cpu_ctx, SECURE);
306 cm_init_my_context(ep_info);
307
308 /*
309 * Adjust secondary cpu entry point for 32 bit images to the
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000310 * end of exception vectors
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800311 */
Anthony Zhou50b328a2017-09-19 16:36:22 +0800312 if ((cpu != 0U) && (reg_width == MODE_RW_32)) {
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800313 INFO("trusty: cpu %d, adjust entry point to 0x%lx\n",
314 cpu, ep_info->pc + (1U << 5));
315 cm_set_elr_el3(SECURE, ep_info->pc + (1U << 5));
316 }
317
318 cm_el1_sysregs_context_restore(SECURE);
Arve Hjønnevågcef22ea2015-08-04 16:19:27 -0700319 fpregs_context_restore(get_fpregs_ctx(cm_get_context(SECURE)));
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800320 cm_set_next_eret_context(SECURE);
321
Anthony Zhou50b328a2017-09-19 16:36:22 +0800322 ctx->saved_security_state = ~0U; /* initial saved state is invalid */
323 (void)trusty_init_context_stack(&ctx->saved_sp, &ctx->secure_stack.end);
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800324
Anthony Zhou50b328a2017-09-19 16:36:22 +0800325 (void)trusty_context_switch_helper(&ctx->saved_sp, &zero_args);
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800326
327 cm_el1_sysregs_context_restore(NON_SECURE);
Arve Hjønnevågcef22ea2015-08-04 16:19:27 -0700328 fpregs_context_restore(get_fpregs_ctx(cm_get_context(NON_SECURE)));
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800329 cm_set_next_eret_context(NON_SECURE);
330
Antonio Nino Diaz41bd97e2018-09-18 13:13:24 +0100331 return 1;
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800332}
333
Arve Hjønnevåg3420e1a2017-11-27 11:05:46 -0800334static void trusty_cpu_suspend(uint32_t off)
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800335{
Anthony Zhou50b328a2017-09-19 16:36:22 +0800336 struct smc_args ret;
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800337
Arve Hjønnevåg3420e1a2017-11-27 11:05:46 -0800338 ret = trusty_context_switch(NON_SECURE, SMC_FC_CPU_SUSPEND, off, 0, 0);
Anthony Zhou50b328a2017-09-19 16:36:22 +0800339 if (ret.r0 != 0U) {
Masahiro Yamadae93a0f42018-02-02 15:09:36 +0900340 INFO("%s: cpu %d, SMC_FC_CPU_SUSPEND returned unexpected value, %lld\n",
Sandrine Bailleux5f665c82016-11-23 09:50:53 +0000341 __func__, plat_my_core_pos(), ret.r0);
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800342 }
343}
344
Arve Hjønnevåg3420e1a2017-11-27 11:05:46 -0800345static void trusty_cpu_resume(uint32_t on)
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800346{
Anthony Zhou50b328a2017-09-19 16:36:22 +0800347 struct smc_args ret;
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800348
Arve Hjønnevåg3420e1a2017-11-27 11:05:46 -0800349 ret = trusty_context_switch(NON_SECURE, SMC_FC_CPU_RESUME, on, 0, 0);
Anthony Zhou50b328a2017-09-19 16:36:22 +0800350 if (ret.r0 != 0U) {
Masahiro Yamadae93a0f42018-02-02 15:09:36 +0900351 INFO("%s: cpu %d, SMC_FC_CPU_RESUME returned unexpected value, %lld\n",
Sandrine Bailleux5f665c82016-11-23 09:50:53 +0000352 __func__, plat_my_core_pos(), ret.r0);
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800353 }
354}
355
Stephen Wolfeea50cd72018-03-29 12:32:08 -0700356static int32_t trusty_cpu_off_handler(u_register_t max_off_lvl)
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800357{
Stephen Wolfeea50cd72018-03-29 12:32:08 -0700358 trusty_cpu_suspend(max_off_lvl);
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800359
360 return 0;
361}
362
Stephen Wolfeea50cd72018-03-29 12:32:08 -0700363static void trusty_cpu_on_finish_handler(u_register_t max_off_lvl)
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800364{
365 struct trusty_cpu_ctx *ctx = get_trusty_ctx();
366
Anthony Zhou50b328a2017-09-19 16:36:22 +0800367 if (ctx->saved_sp == NULL) {
368 (void)trusty_init();
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800369 } else {
Stephen Wolfeea50cd72018-03-29 12:32:08 -0700370 trusty_cpu_resume(max_off_lvl);
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800371 }
372}
373
Stephen Wolfeea50cd72018-03-29 12:32:08 -0700374static void trusty_cpu_suspend_handler(u_register_t max_off_lvl)
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800375{
Stephen Wolfeea50cd72018-03-29 12:32:08 -0700376 trusty_cpu_suspend(max_off_lvl);
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800377}
378
Stephen Wolfeea50cd72018-03-29 12:32:08 -0700379static void trusty_cpu_suspend_finish_handler(u_register_t max_off_lvl)
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800380{
Stephen Wolfeea50cd72018-03-29 12:32:08 -0700381 trusty_cpu_resume(max_off_lvl);
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800382}
383
384static const spd_pm_ops_t trusty_pm = {
385 .svc_off = trusty_cpu_off_handler,
386 .svc_suspend = trusty_cpu_suspend_handler,
387 .svc_on_finish = trusty_cpu_on_finish_handler,
388 .svc_suspend_finish = trusty_cpu_suspend_finish_handler,
389};
390
Arve Hjønnevågafb6f742017-11-28 14:05:30 -0800391void plat_trusty_set_boot_args(aapcs64_params_t *args);
392
Arve Hjønnevåg41ba13f2018-04-11 16:10:53 -0700393#if !defined(TSP_SEC_MEM_SIZE) && defined(BL32_MEM_SIZE)
394#define TSP_SEC_MEM_SIZE BL32_MEM_SIZE
395#endif
396
Arve Hjønnevågafb6f742017-11-28 14:05:30 -0800397#ifdef TSP_SEC_MEM_SIZE
398#pragma weak plat_trusty_set_boot_args
399void plat_trusty_set_boot_args(aapcs64_params_t *args)
400{
401 args->arg0 = TSP_SEC_MEM_SIZE;
402}
403#endif
404
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800405static int32_t trusty_setup(void)
406{
407 entry_point_info_t *ep_info;
Arve Hjønnevågafb6f742017-11-28 14:05:30 -0800408 uint32_t instr;
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800409 uint32_t flags;
Anthony Zhou50b328a2017-09-19 16:36:22 +0800410 int32_t ret;
Arve Hjønnevågddeb2e72018-02-28 17:15:06 -0800411 bool aarch32 = false;
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800412
Varun Wadekarba33a282017-02-23 10:34:06 -0800413 /* Get trusty's entry point info */
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800414 ep_info = bl31_plat_get_next_image_ep_info(SECURE);
Anthony Zhou50b328a2017-09-19 16:36:22 +0800415 if (ep_info == NULL) {
Varun Wadekarbebb0d72018-10-16 15:39:55 -0700416 VERBOSE("Trusty image missing.\n");
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800417 return -1;
418 }
419
Varun Wadekarbe57abb2019-01-03 10:44:22 -0800420 /* memmap first page of trusty's code memory before peeking */
421 ret = mmap_add_dynamic_region(ep_info->pc, /* PA */
422 ep_info->pc, /* VA */
423 PAGE_SIZE, /* size */
424 MT_SECURE | MT_RW_DATA); /* attrs */
425 assert(ret == 0);
426
427 /* peek into trusty's code to see if we have a 32-bit or 64-bit image */
Arve Hjønnevågafb6f742017-11-28 14:05:30 -0800428 instr = *(uint32_t *)ep_info->pc;
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800429
Arve Hjønnevågee8c3032018-02-28 17:18:55 -0800430 if (instr >> 24 == 0xeaU) {
Arve Hjønnevågafb6f742017-11-28 14:05:30 -0800431 INFO("trusty: Found 32 bit image\n");
Arve Hjønnevågddeb2e72018-02-28 17:15:06 -0800432 aarch32 = true;
Arve Hjønnevåg9d31cac2018-03-02 10:10:00 -0800433 } else if (instr >> 8 == 0xd53810U || instr >> 16 == 0x9400U) {
Arve Hjønnevågafb6f742017-11-28 14:05:30 -0800434 INFO("trusty: Found 64 bit image\n");
435 } else {
David Lin72f6fed2019-01-24 14:15:57 -0800436 ERROR("trusty: Found unknown image, 0x%x\n", instr);
437 return -1;
Arve Hjønnevågafb6f742017-11-28 14:05:30 -0800438 }
439
Varun Wadekarbe57abb2019-01-03 10:44:22 -0800440 /* unmap trusty's memory page */
441 (void)mmap_remove_dynamic_region(ep_info->pc, PAGE_SIZE);
442
Arve Hjønnevågafb6f742017-11-28 14:05:30 -0800443 SET_PARAM_HEAD(ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE);
444 if (!aarch32)
445 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
446 DISABLE_ALL_EXCEPTIONS);
447 else
448 ep_info->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
449 SPSR_E_LITTLE,
450 DAIF_FIQ_BIT |
451 DAIF_IRQ_BIT |
452 DAIF_ABT_BIT);
Arve Hjønnevågd1771c62018-03-01 11:38:18 -0800453 (void)memset(&ep_info->args, 0, sizeof(ep_info->args));
Arve Hjønnevågafb6f742017-11-28 14:05:30 -0800454 plat_trusty_set_boot_args(&ep_info->args);
Wayne Lincd712fd2016-05-24 15:28:42 -0700455
Varun Wadekarba33a282017-02-23 10:34:06 -0800456 /* register init handler */
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800457 bl31_register_bl32_init(trusty_init);
458
Varun Wadekarba33a282017-02-23 10:34:06 -0800459 /* register power management hooks */
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800460 psci_register_spd_pm_hook(&trusty_pm);
461
Varun Wadekarba33a282017-02-23 10:34:06 -0800462 /* register interrupt handler */
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800463 flags = 0;
464 set_interrupt_rm_flag(flags, NON_SECURE);
465 ret = register_interrupt_type_handler(INTR_TYPE_S_EL1,
466 trusty_fiq_handler,
467 flags);
Anthony Zhou50b328a2017-09-19 16:36:22 +0800468 if (ret != 0) {
Varun Wadekarbebb0d72018-10-16 15:39:55 -0700469 VERBOSE("trusty: failed to register fiq handler, ret = %d\n", ret);
Anthony Zhou50b328a2017-09-19 16:36:22 +0800470 }
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800471
Arve Hjønnevåg19ad7752017-09-28 14:59:10 -0700472 if (aarch32) {
473 entry_point_info_t *ns_ep_info;
474 uint32_t spsr;
475
476 ns_ep_info = bl31_plat_get_next_image_ep_info(NON_SECURE);
Sandrine Bailleux4cfec802018-03-19 10:41:06 +0100477 if (ns_ep_info == NULL) {
Arve Hjønnevåg19ad7752017-09-28 14:59:10 -0700478 NOTICE("Trusty: non-secure image missing.\n");
479 return -1;
480 }
481 spsr = ns_ep_info->spsr;
482 if (GET_RW(spsr) == MODE_RW_64 && GET_EL(spsr) == MODE_EL2) {
483 spsr &= ~(MODE_EL_MASK << MODE_EL_SHIFT);
484 spsr |= MODE_EL1 << MODE_EL_SHIFT;
485 }
486 if (GET_RW(spsr) == MODE_RW_32 && GET_M32(spsr) == MODE32_hyp) {
487 spsr &= ~(MODE32_MASK << MODE32_SHIFT);
488 spsr |= MODE32_svc << MODE32_SHIFT;
489 }
490 if (spsr != ns_ep_info->spsr) {
491 NOTICE("Trusty: Switch bl33 from EL2 to EL1 (spsr 0x%x -> 0x%x)\n",
492 ns_ep_info->spsr, spsr);
493 ns_ep_info->spsr = spsr;
494 }
495 }
496
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800497 return 0;
498}
499
500/* Define a SPD runtime service descriptor for fast SMC calls */
501DECLARE_RT_SVC(
502 trusty_fast,
503
504 OEN_TOS_START,
505 SMC_ENTITY_SECURE_MONITOR,
506 SMC_TYPE_FAST,
507 trusty_setup,
508 trusty_smc_handler
509);
510
David Cunadoc8833ea2017-04-16 17:15:08 +0100511/* Define a SPD runtime service descriptor for yielding SMC calls */
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800512DECLARE_RT_SVC(
513 trusty_std,
514
Amith43e89d32015-08-19 20:13:12 -0700515 OEN_TAP_START,
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800516 SMC_ENTITY_SECURE_MONITOR,
David Cunadoc8833ea2017-04-16 17:15:08 +0100517 SMC_TYPE_YIELD,
Varun Wadekarc1d2a282016-11-08 15:46:48 -0800518 NULL,
519 trusty_smc_handler
520);