blob: 90623a2731737fd7f73ff4b86284492119d11ebc [file] [log] [blame]
Usama Arifbec5afd2020-04-17 16:13:39 +01001/*
2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <platform_def.h>
10#include <cpu_macros.S>
11
12 .globl plat_arm_calc_core_pos
13 .globl plat_reset_handler
14
15 /* ---------------------------------------------------------------------
16 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
17 *
18 * Function to calculate the core position on TC0.
19 *
20 * (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) +
21 * (CPUId * PLAT_MAX_PE_PER_CPU) +
22 * ThreadId
23 *
24 * which can be simplified as:
25 *
26 * ((ClusterId * PLAT_MAX_CPUS_PER_CLUSTER + CPUId) * PLAT_MAX_PE_PER_CPU)
27 * + ThreadId
28 * ---------------------------------------------------------------------
29 */
30func plat_arm_calc_core_pos
31 /*
32 * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
33 * look as if in a multi-threaded implementation.
34 */
35 tst x0, #MPIDR_MT_MASK
36 lsl x3, x0, #MPIDR_AFFINITY_BITS
37 csel x3, x3, x0, eq
38
39 /* Extract individual affinity fields from MPIDR */
40 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
41 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
42 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
43
44 /* Compute linear position */
45 mov x4, #PLAT_MAX_CPUS_PER_CLUSTER
46 madd x1, x2, x4, x1
47 mov x5, #PLAT_MAX_PE_PER_CPU
48 madd x0, x1, x5, x0
49 ret
50endfunc plat_arm_calc_core_pos
51
52 /* -----------------------------------------------------
53 * void plat_reset_handler(void);
54 *
55 * Determine the CPU MIDR and disable power down bit for
56 * that CPU.
57 * -----------------------------------------------------
58 */
59func plat_reset_handler
60 ret
61endfunc plat_reset_handler