blob: d7f088094b884294efd77596dae1c1e9ad5002b3 [file] [log] [blame]
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +02001/*
2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +02007#include <assert.h>
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +02008#include <string.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <arch.h>
11#include <arch_helpers.h>
12#include <common/debug.h>
13#include <lib/bakery_lock.h>
14#include <lib/mmio.h>
15#include <lib/xlat_tables/xlat_tables_v2.h>
16
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +020017#include "iic_dvfs.h"
18#include "rcar_def.h"
19#include "rcar_private.h"
Marek Vasut4bc543c2018-12-28 20:15:33 +010020#include "micro_delay.h"
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +020021#include "pwrc.h"
22
23/*
24 * Someday there will be a generic power controller api. At the moment each
25 * platform has its own pwrc so just exporting functions should be acceptable.
26 */
27RCAR_INSTANTIATE_LOCK
28
29#define WUP_IRQ_SHIFT (0U)
30#define WUP_FIQ_SHIFT (8U)
31#define WUP_CSD_SHIFT (16U)
32#define BIT_SOFTRESET (1U<<15)
33#define BIT_CA53_SCU (1U<<21)
34#define BIT_CA57_SCU (1U<<12)
35#define REQ_RESUME (1U<<1)
36#define REQ_OFF (1U<<0)
37#define STATUS_PWRUP (1U<<4)
38#define STATUS_PWRDOWN (1U<<0)
39#define STATE_CA57_CPU (27U)
40#define STATE_CA53_CPU (22U)
41#define MODE_L2_DOWN (0x00000002U)
42#define CPU_PWR_OFF (0x00000003U)
43#define RCAR_PSTR_MASK (0x00000003U)
44#define ST_ALL_STANDBY (0x00003333U)
45/* Suspend to ram */
46#define DBSC4_REG_BASE (0xE6790000U)
47#define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U)
48#define DBSC4_REG_DBACEN (DBSC4_REG_BASE + 0x0200U)
49#define DBSC4_REG_DBCMD (DBSC4_REG_BASE + 0x0208U)
50#define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U)
51#define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U)
52#define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + 0x0424U)
53#define DBSC4_REG_DBPDLK0 (DBSC4_REG_BASE + 0x0620U)
54#define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U)
55#define DBSC4_REG_DBPDRGD0 (DBSC4_REG_BASE + 0x0628U)
56#define DBSC4_REG_DBCAM0CTRL0 (DBSC4_REG_BASE + 0x0940U)
57#define DBSC4_REG_DBCAM0STAT0 (DBSC4_REG_BASE + 0x0980U)
58#define DBSC4_REG_DBCAM1STAT0 (DBSC4_REG_BASE + 0x0990U)
59#define DBSC4_REG_DBCAM2STAT0 (DBSC4_REG_BASE + 0x09A0U)
60#define DBSC4_REG_DBCAM3STAT0 (DBSC4_REG_BASE + 0x09B0U)
61#define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0))
62#define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0))
63#define DBSC4_BIT_DBCAMxSTAT0 (0x00000001U)
64#define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U)
65#define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U)
66#define DBSC4_SET_DBCMD_OPC_PD (0x08000000U)
67#define DBSC4_SET_DBCMD_OPC_MRW (0x0E000000U)
68#define DBSC4_SET_DBCMD_CH_ALL (0x00800000U)
69#define DBSC4_SET_DBCMD_RANK_ALL (0x00040000U)
70#define DBSC4_SET_DBCMD_ARG_ALL (0x00000010U)
71#define DBSC4_SET_DBCMD_ARG_ENTER (0x00000000U)
72#define DBSC4_SET_DBCMD_ARG_MRW_ODTC (0x00000B00U)
73#define DBSC4_SET_DBSYSCNT0_WRITE_ENABLE (0x00001234U)
74#define DBSC4_SET_DBSYSCNT0_WRITE_DISABLE (0x00000000U)
75#define DBSC4_SET_DBPDLK0_PHY_ACCESS (0x0000A55AU)
76#define DBSC4_SET_DBPDRGA0_ACIOCR0 (0x0000001AU)
77#define DBSC4_SET_DBPDRGD0_ACIOCR0 (0x33C03C11U)
78#define DBSC4_SET_DBPDRGA0_DXCCR (0x00000020U)
79#define DBSC4_SET_DBPDRGD0_DXCCR (0x00181006U)
80#define DBSC4_SET_DBPDRGA0_PGCR1 (0x00000003U)
81#define DBSC4_SET_DBPDRGD0_PGCR1 (0x0380C600U)
82#define DBSC4_SET_DBPDRGA0_ACIOCR1 (0x0000001BU)
83#define DBSC4_SET_DBPDRGD0_ACIOCR1 (0xAAAAAAAAU)
84#define DBSC4_SET_DBPDRGA0_ACIOCR3 (0x0000001DU)
85#define DBSC4_SET_DBPDRGD0_ACIOCR3 (0xAAAAAAAAU)
86#define DBSC4_SET_DBPDRGA0_ACIOCR5 (0x0000001FU)
87#define DBSC4_SET_DBPDRGD0_ACIOCR5 (0x000000AAU)
88#define DBSC4_SET_DBPDRGA0_DX0GCR2 (0x000000A2U)
89#define DBSC4_SET_DBPDRGD0_DX0GCR2 (0xAAAA0000U)
90#define DBSC4_SET_DBPDRGA0_DX1GCR2 (0x000000C2U)
91#define DBSC4_SET_DBPDRGD0_DX1GCR2 (0xAAAA0000U)
92#define DBSC4_SET_DBPDRGA0_DX2GCR2 (0x000000E2U)
93#define DBSC4_SET_DBPDRGD0_DX2GCR2 (0xAAAA0000U)
94#define DBSC4_SET_DBPDRGA0_DX3GCR2 (0x00000102U)
95#define DBSC4_SET_DBPDRGD0_DX3GCR2 (0xAAAA0000U)
96#define DBSC4_SET_DBPDRGA0_ZQCR (0x00000090U)
97#define DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 (0x04058904U)
98#define DBSC4_SET_DBPDRGD0_ZQCR_MD19_1 (0x04058A04U)
99#define DBSC4_SET_DBPDRGA0_DX0GCR0 (0x000000A0U)
100#define DBSC4_SET_DBPDRGD0_DX0GCR0 (0x7C0002E5U)
101#define DBSC4_SET_DBPDRGA0_DX1GCR0 (0x000000C0U)
102#define DBSC4_SET_DBPDRGD0_DX1GCR0 (0x7C0002E5U)
103#define DBSC4_SET_DBPDRGA0_DX2GCR0 (0x000000E0U)
104#define DBSC4_SET_DBPDRGD0_DX2GCR0 (0x7C0002E5U)
105#define DBSC4_SET_DBPDRGA0_DX3GCR0 (0x00000100U)
106#define DBSC4_SET_DBPDRGD0_DX3GCR0 (0x7C0002E5U)
107#define DBSC4_SET_DBPDRGA0_DX0GCR1 (0x000000A1U)
108#define DBSC4_SET_DBPDRGD0_DX0GCR1 (0x55550000U)
109#define DBSC4_SET_DBPDRGA0_DX1GCR1 (0x000000C1U)
110#define DBSC4_SET_DBPDRGD0_DX1GCR1 (0x55550000U)
111#define DBSC4_SET_DBPDRGA0_DX2GCR1 (0x000000E1U)
112#define DBSC4_SET_DBPDRGD0_DX2GCR1 (0x55550000U)
113#define DBSC4_SET_DBPDRGA0_DX3GCR1 (0x00000101U)
114#define DBSC4_SET_DBPDRGD0_DX3GCR1 (0x55550000U)
115#define DBSC4_SET_DBPDRGA0_DX0GCR3 (0x000000A3U)
116#define DBSC4_SET_DBPDRGD0_DX0GCR3 (0x00008484U)
117#define DBSC4_SET_DBPDRGA0_DX1GCR3 (0x000000C3U)
118#define DBSC4_SET_DBPDRGD0_DX1GCR3 (0x00008484U)
119#define DBSC4_SET_DBPDRGA0_DX2GCR3 (0x000000E3U)
120#define DBSC4_SET_DBPDRGD0_DX2GCR3 (0x00008484U)
121#define DBSC4_SET_DBPDRGA0_DX3GCR3 (0x00000103U)
122#define DBSC4_SET_DBPDRGD0_DX3GCR3 (0x00008484U)
123#define RST_BASE (0xE6160000U)
124#define RST_MODEMR (RST_BASE + 0x0060U)
125#define RST_MODEMR_BIT0 (0x00000001U)
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +0200126
127#if PMIC_ROHM_BD9571
128#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
129#define PMIC_BKUP_MODE_CNT (0x20U)
130#define PMIC_QLLM_CNT (0x27U)
131#define PMIC_RETRY_MAX (100U)
132#endif
133#define SCTLR_EL3_M_BIT ((uint32_t)1U << 0)
134#define RCAR_CA53CPU_NUM_MAX (4U)
135#define RCAR_CA57CPU_NUM_MAX (4U)
136#define IS_A53A57(c) ((c) == RCAR_CLUSTER_A53A57)
137#define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57)
138#define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53)
139
140#ifndef __ASSEMBLY__
141IMPORT_SYM(unsigned long, __system_ram_start__, SYSTEM_RAM_START);
142IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END);
143IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START);
144#endif
145
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +0200146uint32_t rcar_pwrc_status(uint64_t mpidr)
147{
148 uint32_t ret = 0;
149 uint64_t cm, cpu;
150 uint32_t reg;
151 uint32_t c;
152
153 rcar_lock_get();
154
155 c = rcar_pwrc_get_cluster();
156 cm = mpidr & MPIDR_CLUSTER_MASK;
157
158 if (!IS_A53A57(c) && cm != 0) {
159 ret = RCAR_INVALID;
160 goto done;
161 }
162
163 reg = mmio_read_32(RCAR_PRR);
164 cpu = mpidr & MPIDR_CPU_MASK;
165
166 if (IS_CA53(c))
167 if (reg & (1 << (STATE_CA53_CPU + cpu)))
168 ret = RCAR_INVALID;
169 if (IS_CA57(c))
170 if (reg & (1 << (STATE_CA57_CPU + cpu)))
171 ret = RCAR_INVALID;
172done:
173 rcar_lock_release();
174
175 return ret;
176}
177
178static void scu_power_up(uint64_t mpidr)
179{
180 uintptr_t reg_pwrsr, reg_cpumcr, reg_pwron, reg_pwrer;
181 uint32_t c, sysc_reg_bit;
182
183 c = rcar_pwrc_get_mpidr_cluster(mpidr);
184 reg_cpumcr = IS_CA57(c) ? RCAR_CA57CPUCMCR : RCAR_CA53CPUCMCR;
185 sysc_reg_bit = IS_CA57(c) ? BIT_CA57_SCU : BIT_CA53_SCU;
186 reg_pwron = IS_CA57(c) ? RCAR_PWRONCR5 : RCAR_PWRONCR3;
187 reg_pwrer = IS_CA57(c) ? RCAR_PWRER5 : RCAR_PWRER3;
188 reg_pwrsr = IS_CA57(c) ? RCAR_PWRSR5 : RCAR_PWRSR3;
189
190 if ((mmio_read_32(reg_pwrsr) & STATUS_PWRDOWN) == 0)
191 return;
192
193 if (mmio_read_32(reg_cpumcr) != 0)
194 mmio_write_32(reg_cpumcr, 0);
195
196 mmio_setbits_32(RCAR_SYSCIER, sysc_reg_bit);
197 mmio_setbits_32(RCAR_SYSCIMR, sysc_reg_bit);
198
199 do {
200 while ((mmio_read_32(RCAR_SYSCSR) & REQ_RESUME) == 0)
201 ;
202 mmio_write_32(reg_pwron, 1);
203 } while (mmio_read_32(reg_pwrer) & 1);
204
205 while ((mmio_read_32(RCAR_SYSCISR) & sysc_reg_bit) == 0)
206 ;
207 mmio_write_32(RCAR_SYSCISR, sysc_reg_bit);
208 while ((mmio_read_32(reg_pwrsr) & STATUS_PWRUP) == 0)
209 ;
210}
211
212void rcar_pwrc_cpuon(uint64_t mpidr)
213{
214 uint32_t res_data, on_data;
215 uintptr_t res_reg, on_reg;
216 uint32_t limit, c;
217 uint64_t cpu;
218
219 rcar_lock_get();
220
221 c = rcar_pwrc_get_mpidr_cluster(mpidr);
222 res_reg = IS_CA53(c) ? RCAR_CA53RESCNT : RCAR_CA57RESCNT;
223 on_reg = IS_CA53(c) ? RCAR_CA53WUPCR : RCAR_CA57WUPCR;
224 limit = IS_CA53(c) ? 0x5A5A0000 : 0xA5A50000;
225
226 res_data = mmio_read_32(res_reg) | limit;
227 scu_power_up(mpidr);
228 cpu = mpidr & MPIDR_CPU_MASK;
229 on_data = 1 << cpu;
230 mmio_write_32(RCAR_CPGWPR, ~on_data);
231 mmio_write_32(on_reg, on_data);
232 mmio_write_32(res_reg, res_data & (~(1 << (3 - cpu))));
233
234 rcar_lock_release();
235}
236
237void rcar_pwrc_cpuoff(uint64_t mpidr)
238{
239 uint32_t c;
240 uintptr_t reg;
241 uint64_t cpu;
242
243 rcar_lock_get();
244
245 cpu = mpidr & MPIDR_CPU_MASK;
246 c = rcar_pwrc_get_mpidr_cluster(mpidr);
247 reg = IS_CA53(c) ? RCAR_CA53CPU0CR : RCAR_CA57CPU0CR;
248
249 if (read_mpidr_el1() != mpidr)
250 panic();
251
252 mmio_write_32(RCAR_CPGWPR, ~CPU_PWR_OFF);
253 mmio_write_32(reg + cpu * 0x0010, CPU_PWR_OFF);
254
255 rcar_lock_release();
256}
257
258void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr)
259{
260 uint32_t c, shift_irq, shift_fiq;
261 uintptr_t reg;
262 uint64_t cpu;
263
264 rcar_lock_get();
265
266 cpu = mpidr & MPIDR_CPU_MASK;
267 c = rcar_pwrc_get_mpidr_cluster(mpidr);
268 reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57;
269
270 shift_irq = WUP_IRQ_SHIFT + cpu;
271 shift_fiq = WUP_FIQ_SHIFT + cpu;
272
273 mmio_write_32(reg, ~((uint32_t) 1 << shift_irq) &
274 ~((uint32_t) 1 << shift_fiq));
275 rcar_lock_release();
276}
277
278void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr)
279{
280 uint32_t c, shift_irq, shift_fiq;
281 uintptr_t reg;
282 uint64_t cpu;
283
284 rcar_lock_get();
285
286 cpu = mpidr & MPIDR_CPU_MASK;
287 c = rcar_pwrc_get_mpidr_cluster(mpidr);
288 reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57;
289
290 shift_irq = WUP_IRQ_SHIFT + cpu;
291 shift_fiq = WUP_FIQ_SHIFT + cpu;
292
293 mmio_write_32(reg, ((uint32_t) 1 << shift_irq) |
294 ((uint32_t) 1 << shift_fiq));
295 rcar_lock_release();
296}
297
298void rcar_pwrc_clusteroff(uint64_t mpidr)
299{
300 uint32_t c, product, cut, reg;
301 uintptr_t dst;
302
303 rcar_lock_get();
304
305 reg = mmio_read_32(RCAR_PRR);
306 product = reg & RCAR_PRODUCT_MASK;
307 cut = reg & RCAR_CUT_MASK;
308
309 c = rcar_pwrc_get_mpidr_cluster(mpidr);
310 dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
311
312 if (RCAR_PRODUCT_M3 == product && cut <= RCAR_M3_CUT_VER11)
313 goto done;
314
315 if (RCAR_PRODUCT_H3 == product && cut <= RCAR_CUT_VER20)
316 goto done;
317
318 /* all of the CPUs in the cluster is in the CoreStandby mode */
319 mmio_write_32(dst, MODE_L2_DOWN);
320done:
321 rcar_lock_release();
322}
323
324#if !PMIC_ROHM_BD9571
325void rcar_pwrc_system_reset(void)
326{
327 mmio_write_32(RCAR_SRESCR, 0x5AA50000U | BIT_SOFTRESET);
328}
329#endif /* PMIC_ROHM_BD9571 */
330
331#define RST_CA53_CPU0_BARH (0xE6160080U)
332#define RST_CA53_CPU0_BARL (0xE6160084U)
333#define RST_CA57_CPU0_BARH (0xE61600C0U)
334#define RST_CA57_CPU0_BARL (0xE61600C4U)
335
336void rcar_pwrc_setup(void)
337{
338 uintptr_t rst_barh;
339 uintptr_t rst_barl;
340 uint32_t i, j;
341 uint64_t reset = (uint64_t) (&plat_secondary_reset) & 0xFFFFFFFF;
342
343 const uint32_t cluster[PLATFORM_CLUSTER_COUNT] = {
344 RCAR_CLUSTER_CA53,
345 RCAR_CLUSTER_CA57
346 };
347 const uintptr_t reg_barh[PLATFORM_CLUSTER_COUNT] = {
348 RST_CA53_CPU0_BARH,
349 RST_CA57_CPU0_BARH
350 };
351 const uintptr_t reg_barl[PLATFORM_CLUSTER_COUNT] = {
352 RST_CA53_CPU0_BARL,
353 RST_CA57_CPU0_BARL
354 };
355
356 for (i = 0; i < PLATFORM_CLUSTER_COUNT; i++) {
357 rst_barh = reg_barh[i];
358 rst_barl = reg_barl[i];
359 for (j = 0; j < rcar_pwrc_get_cpu_num(cluster[i]); j++) {
360 mmio_write_32(rst_barh, 0);
361 mmio_write_32(rst_barl, (uint32_t) reset);
362 rst_barh += 0x10;
363 rst_barl += 0x10;
364 }
365 }
366
367 rcar_lock_init();
368}
369
370#if RCAR_SYSTEM_SUSPEND
371#define DBCAM_FLUSH(__bit) \
372do { \
373 ; \
374} while (!(mmio_read_32(DBSC4_REG_DBCAM##__bit##STAT0) & DBSC4_BIT_DBCAMxSTAT0))
375
376
377static void __attribute__ ((section(".system_ram")))
378 rcar_pwrc_set_self_refresh(void)
379{
380 uint32_t reg = mmio_read_32(RCAR_PRR);
381 uint32_t cut, product;
382
383 product = reg & RCAR_PRODUCT_MASK;
384 cut = reg & RCAR_CUT_MASK;
385
386 if (product == RCAR_PRODUCT_M3)
387 goto self_refresh;
388
389 if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
390 goto self_refresh;
391
392 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
393
394self_refresh:
395
396 /* Set the Self-Refresh mode */
397 mmio_write_32(DBSC4_REG_DBACEN, 0);
398
399 if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
Marek Vasut4bc543c2018-12-28 20:15:33 +0100400 rcar_micro_delay(100);
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +0200401 else if (product == RCAR_PRODUCT_H3) {
402 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
403 DBCAM_FLUSH(0);
404 DBCAM_FLUSH(1);
405 DBCAM_FLUSH(2);
406 DBCAM_FLUSH(3);
407 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
408 } else if (product == RCAR_PRODUCT_M3) {
409 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
410 DBCAM_FLUSH(0);
411 DBCAM_FLUSH(1);
412 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
413 } else {
414 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
415 DBCAM_FLUSH(0);
416 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
417 }
418
419 /* Set the SDRAM calibration configuration register */
420 mmio_write_32(DBSC4_REG_DBCALCNF, 0);
421
422 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL |
423 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL;
424 mmio_write_32(DBSC4_REG_DBCMD, reg);
425 while (mmio_read_32(DBSC4_REG_DBWAIT))
426 ;
427
428 /* Self-Refresh entry command */
429 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL |
430 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
431 mmio_write_32(DBSC4_REG_DBCMD, reg);
432 while (mmio_read_32(DBSC4_REG_DBWAIT))
433 ;
434
435 /* Mode Register Write command. (ODT disabled) */
436 reg = DBSC4_SET_DBCMD_OPC_MRW | DBSC4_SET_DBCMD_CH_ALL |
437 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_MRW_ODTC;
438 mmio_write_32(DBSC4_REG_DBCMD, reg);
439 while (mmio_read_32(DBSC4_REG_DBWAIT))
440 ;
441
442 /* Power Down entry command */
443 reg = DBSC4_SET_DBCMD_OPC_PD | DBSC4_SET_DBCMD_CH_ALL |
444 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
445 mmio_write_32(DBSC4_REG_DBCMD, reg);
446 while (mmio_read_32(DBSC4_REG_DBWAIT))
447 ;
448
449 /* Set the auto-refresh enable register */
450 mmio_write_32(DBSC4_REG_DBRFEN, 0U);
Marek Vasut4bc543c2018-12-28 20:15:33 +0100451 rcar_micro_delay(1U);
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +0200452
453 if (product == RCAR_PRODUCT_M3)
454 return;
455
456 if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
457 return;
458
459 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
460}
461
462static void __attribute__ ((section(".system_ram")))
463 rcar_pwrc_set_self_refresh_e3(void)
464{
465 uint32_t ddr_md;
466 uint32_t reg;
467
468 ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & RST_MODEMR_BIT0;
469
470 /* Write enable */
471 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
472 mmio_write_32(DBSC4_REG_DBACEN, 0);
473 DBCAM_FLUSH(0);
474
475 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL |
476 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL;
477 mmio_write_32(DBSC4_REG_DBCMD, reg);
478 while (mmio_read_32(DBSC4_REG_DBWAIT))
479 ;
480
481 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL |
482 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
483 mmio_write_32(DBSC4_REG_DBCMD, reg);
484 while (mmio_read_32(DBSC4_REG_DBWAIT))
485 ;
486
487 /* Set the auto-refresh enable register */
488 /* Set the ARFEN bit to 0 in the DBRFEN */
489 mmio_write_32(DBSC4_REG_DBRFEN, 0);
490
491 mmio_write_32(DBSC4_REG_DBPDLK0, DBSC4_SET_DBPDLK0_PHY_ACCESS);
492
493 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR0);
494 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR0);
495
496 /* DDR_DXCCR */
497 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DXCCR);
498 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DXCCR);
499
500 /* DDR_PGCR1 */
501 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_PGCR1);
502 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_PGCR1);
503
504 /* DDR_ACIOCR1 */
505 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR1);
506 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR1);
507
508 /* DDR_ACIOCR3 */
509 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR3);
510 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR3);
511
512 /* DDR_ACIOCR5 */
513 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR5);
514 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR5);
515
516 /* DDR_DX0GCR2 */
517 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR2);
518 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR2);
519
520 /* DDR_DX1GCR2 */
521 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR2);
522 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR2);
523
524 /* DDR_DX2GCR2 */
525 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR2);
526 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR2);
527
528 /* DDR_DX3GCR2 */
529 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR2);
530 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR2);
531
532 /* DDR_ZQCR */
533 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ZQCR);
534
535 mmio_write_32(DBSC4_REG_DBPDRGD0, ddr_md == 0 ?
536 DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 :
537 DBSC4_SET_DBPDRGD0_ZQCR_MD19_1);
538
539 /* DDR_DX0GCR0 */
540 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR0);
541 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR0);
542
543 /* DDR_DX1GCR0 */
544 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR0);
545 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR0);
546
547 /* DDR_DX2GCR0 */
548 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR0);
549 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR0);
550
551 /* DDR_DX3GCR0 */
552 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR0);
553 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR0);
554
555 /* DDR_DX0GCR1 */
556 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR1);
557 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR1);
558
559 /* DDR_DX1GCR1 */
560 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR1);
561 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR1);
562
563 /* DDR_DX2GCR1 */
564 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR1);
565 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR1);
566
567 /* DDR_DX3GCR1 */
568 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR1);
569 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR1);
570
571 /* DDR_DX0GCR3 */
572 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR3);
573 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR3);
574
575 /* DDR_DX1GCR3 */
576 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR3);
577 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR3);
578
579 /* DDR_DX2GCR3 */
580 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR3);
581 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR3);
582
583 /* DDR_DX3GCR3 */
584 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR3);
585 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR3);
586
587 /* Write disable */
588 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
589}
590
591void __attribute__ ((section(".system_ram"))) __attribute__ ((noinline))
592 rcar_pwrc_go_suspend_to_ram(void)
593{
594#if PMIC_ROHM_BD9571
595 int32_t rc = -1, qllm = -1;
596 uint8_t mode;
597 uint32_t i;
598#endif
599 uint32_t reg, product;
600
601 reg = mmio_read_32(RCAR_PRR);
602 product = reg & RCAR_PRODUCT_MASK;
603
604 if (product != RCAR_PRODUCT_E3)
605 rcar_pwrc_set_self_refresh();
606 else
607 rcar_pwrc_set_self_refresh_e3();
608
609#if PMIC_ROHM_BD9571
610 /* Set QLLM Cnt Disable */
611 for (i = 0; (i < PMIC_RETRY_MAX) && (qllm != 0); i++)
612 qllm = rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, 0);
613
614 /* Set trigger of power down to PMIV */
615 for (i = 0; (i < PMIC_RETRY_MAX) && (rc != 0) && (qllm == 0); i++) {
616 rc = rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode);
617 if (rc == 0) {
618 mode |= BIT_BKUP_CTRL_OUT;
619 rc = rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode);
620 }
621 }
622#endif
623 wfi();
624
625 while (1)
626 ;
627}
628
629void rcar_pwrc_set_suspend_to_ram(void)
630{
631 uintptr_t jump = (uintptr_t) &rcar_pwrc_go_suspend_to_ram;
632 uintptr_t stack = (uintptr_t) (DEVICE_SRAM_STACK_BASE +
633 DEVICE_SRAM_STACK_SIZE);
634 uint32_t sctlr;
635
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +0200636 rcar_pwrc_save_generic_timer(rcar_stack_generic_timer);
637
638 /* disable MMU */
639 sctlr = (uint32_t) read_sctlr_el3();
640 sctlr &= (uint32_t) ~SCTLR_EL3_M_BIT;
641 write_sctlr_el3((uint64_t) sctlr);
642
643 rcar_pwrc_switch_stack(jump, stack, NULL);
644}
645
646void rcar_pwrc_init_suspend_to_ram(void)
647{
648#if PMIC_ROHM_BD9571
649 uint8_t mode;
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +0200650
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +0200651 if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode))
652 panic();
653
654 mode &= (uint8_t) (~BIT_BKUP_CTRL_OUT);
655 if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode))
656 panic();
657#endif
658}
659
660void rcar_pwrc_suspend_to_ram(void)
661{
662#if RCAR_SYSTEM_RESET_KEEPON_DDR
663 int32_t error;
664
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +0200665 error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0);
666 if (error) {
667 ERROR("Failed send KEEP10 init ret=%d \n", error);
668 return;
669 }
670#endif
671 rcar_pwrc_set_suspend_to_ram();
672}
673#endif
674
675void rcar_pwrc_code_copy_to_system_ram(void)
676{
677 int ret __attribute__ ((unused)); /* in assert */
678 uint32_t attr;
679 struct device_sram_t {
680 uintptr_t base;
681 size_t len;
682 } sram = {
683 .base = (uintptr_t) DEVICE_SRAM_BASE,
684 .len = DEVICE_SRAM_SIZE,
685 };
686 struct ddr_code_t {
687 void *base;
688 size_t len;
689 } code = {
690 .base = (void *) SRAM_COPY_START,
691 .len = SYSTEM_RAM_END - SYSTEM_RAM_START,
692 };
693
694 attr = MT_MEMORY | MT_RW | MT_SECURE | MT_EXECUTE_NEVER;
695 ret = xlat_change_mem_attributes(sram.base, sram.len, attr);
696 assert(ret == 0);
697
698 memcpy((void *)sram.base, code.base, code.len);
699 flush_dcache_range((uint64_t) sram.base, code.len);
700
701 /* Invalidate instruction cache */
702 plat_invalidate_icache();
703 dsb();
704 isb();
705
706 attr = MT_MEMORY | MT_RO | MT_SECURE | MT_EXECUTE;
707 ret = xlat_change_mem_attributes(sram.base, sram.len, attr);
708 assert(ret == 0);
709}
710
711uint32_t rcar_pwrc_get_cluster(void)
712{
713 uint32_t reg;
714
715 reg = mmio_read_32(RCAR_PRR);
716
717 if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
718 return RCAR_CLUSTER_CA57;
719
720 if (reg & (1 << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
721 return RCAR_CLUSTER_CA53;
722
723 return RCAR_CLUSTER_A53A57;
724}
725
726uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr)
727{
728 uint32_t c = rcar_pwrc_get_cluster();
729
730 if (IS_A53A57(c)) {
731 if (mpidr & MPIDR_CLUSTER_MASK)
732 return RCAR_CLUSTER_CA53;
733
734 return RCAR_CLUSTER_CA57;
735 }
736
737 return c;
738}
739
740uint32_t rcar_pwrc_get_cpu_num(uint32_t c)
741{
742 uint32_t reg = mmio_read_32(RCAR_PRR);
743 uint32_t count = 0, i;
744
745 if (IS_A53A57(c) || IS_CA53(c)) {
746 if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
747 goto count_ca57;
748
749 for (i = 0; i < RCAR_CA53CPU_NUM_MAX; i++) {
750 if (reg & (1 << (STATE_CA53_CPU + i)))
751 continue;
752 count++;
753 }
754 }
755
756count_ca57:
757 if (IS_A53A57(c) || IS_CA57(c)) {
758 if (reg & (1 << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
759 goto done;
760
761 for (i = 0; i < RCAR_CA57CPU_NUM_MAX; i++) {
762 if (reg & (1 << (STATE_CA57_CPU + i)))
763 continue;
764 count++;
765 }
766 }
767
768done:
769 return count;
770}
Marek Vasut122555f2019-01-05 16:21:14 +0100771
772int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr)
773{
774 uint64_t i;
775 uint64_t j;
776 uint64_t cpu_count;
777 uintptr_t reg_PSTR;
778 uint32_t status;
779 uint64_t my_cpu;
780 int32_t rtn;
781 uint32_t my_cluster_type;
782
783 const uint32_t cluster_type[PLATFORM_CLUSTER_COUNT] = {
784 RCAR_CLUSTER_CA53,
785 RCAR_CLUSTER_CA57
786 };
787 const uintptr_t registerPSTR[PLATFORM_CLUSTER_COUNT] = {
788 RCAR_CA53PSTR,
789 RCAR_CA57PSTR
790 };
791
792 my_cluster_type = rcar_pwrc_get_cluster();
793
794 rtn = 0;
795 my_cpu = mpidr & ((uint64_t)(MPIDR_CPU_MASK));
796 for (i = 0U; i < ((uint64_t)(PLATFORM_CLUSTER_COUNT)); i++) {
797 cpu_count = rcar_pwrc_get_cpu_num(cluster_type[i]);
798 reg_PSTR = registerPSTR[i];
799 for (j = 0U; j < cpu_count; j++) {
800 if ((my_cluster_type != cluster_type[i]) || (my_cpu != j)) {
801 status = mmio_read_32(reg_PSTR) >> (j * 4U);
802 if ((status & 0x00000003U) == 0U) {
803 rtn--;
804 }
805 }
806 }
807 }
808 return (rtn);
809
810}