Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 9 | |
| 10 | #include <arm_def.h> |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 11 | #include <css_def.h> |
Antonio Nino Diaz | a320ecd | 2019-01-15 14:19:50 +0000 | [diff] [blame] | 12 | #include <v2m_def.h> |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 13 | |
Deepak Pandey | b66a18e | 2018-12-18 17:10:24 +0530 | [diff] [blame] | 14 | /* UART related constants */ |
| 15 | #define PLAT_ARM_BOOT_UART_BASE 0x2A400000 |
| 16 | #define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000 |
| 17 | |
| 18 | #define PLAT_ARM_BL31_RUN_UART_BASE 0x2A410000 |
| 19 | #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 50000000 |
| 20 | |
| 21 | #define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000 |
| 22 | #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000 |
| 23 | |
| 24 | #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE |
| 25 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ |
| 26 | |
| 27 | #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) |
| 28 | |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 29 | #if CSS_USE_SCMI_SDS_DRIVER |
| 30 | #define N1SDP_SCMI_PAYLOAD_BASE 0x45400000 |
| 31 | #else |
| 32 | #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000 |
| 33 | #endif |
| 34 | |
| 35 | #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ |
| 36 | #define PLAT_ARM_MAX_BL31_SIZE 0X20000 |
| 37 | |
| 38 | |
| 39 | /******************************************************************************* |
| 40 | * N1SDP topology related constants |
| 41 | ******************************************************************************/ |
| 42 | #define N1SDP_MAX_CPUS_PER_CLUSTER 2 |
| 43 | #define PLAT_ARM_CLUSTER_COUNT 2 |
| 44 | #define N1SDP_MAX_PE_PER_CPU 1 |
| 45 | |
| 46 | #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ |
| 47 | N1SDP_MAX_CPUS_PER_CLUSTER * \ |
| 48 | N1SDP_MAX_PE_PER_CPU) |
| 49 | |
Chandni Cherukuri | 0fdcbc0 | 2018-10-16 15:19:54 +0530 | [diff] [blame] | 50 | /* System power domain level */ |
| 51 | #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 52 | |
| 53 | /* |
| 54 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 55 | * plat_arm_mmap array defined for each BL stage. |
| 56 | */ |
| 57 | #define PLAT_ARM_MMAP_ENTRIES 3 |
| 58 | #define MAX_XLAT_TABLES 4 |
| 59 | |
| 60 | #define PLATFORM_STACK_SIZE 0x400 |
| 61 | |
| 62 | #define PLAT_ARM_NSTIMER_FRAME_ID 0 |
| 63 | #define PLAT_CSS_MHU_BASE 0x45000000 |
| 64 | #define PLAT_MAX_PWR_LVL 1 |
| 65 | |
| 66 | #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ |
| 67 | CSS_IRQ_MHU |
| 68 | #define PLAT_ARM_G0_IRQS ARM_G0_IRQS |
| 69 | |
| 70 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) |
| 71 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 72 | |
| 73 | |
| 74 | #define N1SDP_DEVICE_BASE (0x20000000) |
Deepak Pandey | b66a18e | 2018-12-18 17:10:24 +0530 | [diff] [blame] | 75 | #define N1SDP_DEVICE_SIZE (0x30000000) |
Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 76 | #define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \ |
| 77 | N1SDP_DEVICE_BASE, \ |
| 78 | N1SDP_DEVICE_SIZE, \ |
| 79 | MT_DEVICE | MT_RW | MT_SECURE) |
| 80 | |
| 81 | /* GIC related constants */ |
| 82 | #define PLAT_ARM_GICD_BASE 0x30000000 |
| 83 | #define PLAT_ARM_GICC_BASE 0x2C000000 |
| 84 | #define PLAT_ARM_GICR_BASE 0x300C0000 |
| 85 | |
| 86 | /* Platform ID address */ |
| 87 | #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 88 | |
| 89 | #endif /* PLATFORM_DEF_H */ |