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Tony Xief6118cc2016-01-15 17:17:32 +08001/*
Deepika Bhavnani73fa2d22019-12-13 10:48:54 -06002 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
Tony Xief6118cc2016-01-15 17:17:32 +08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Tony Xief6118cc2016-01-15 17:17:32 +08005 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Tony Xief6118cc2016-01-15 17:17:32 +08009
10#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/utils_def.h>
12#include <plat/common/common_def.h>
13
Xing Zhengc39aacd2016-12-22 18:34:14 +080014#include <bl31_param.h>
Tony Xief6118cc2016-01-15 17:17:32 +080015#include <rk3399_def.h>
16
Tony Xief6118cc2016-01-15 17:17:32 +080017/*******************************************************************************
18 * Platform binary types for linking
19 ******************************************************************************/
20#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
21#define PLATFORM_LINKER_ARCH aarch64
22
23/*******************************************************************************
24 * Generic platform constants
25 ******************************************************************************/
26
27/* Size of cacheable stacks */
Antonio Nino Diaz58230902018-09-24 17:16:20 +010028#if defined(IMAGE_BL1)
Tony Xief6118cc2016-01-15 17:17:32 +080029#define PLATFORM_STACK_SIZE 0x440
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090030#elif defined(IMAGE_BL2)
Tony Xief6118cc2016-01-15 17:17:32 +080031#define PLATFORM_STACK_SIZE 0x400
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090032#elif defined(IMAGE_BL31)
Tony Xief6118cc2016-01-15 17:17:32 +080033#define PLATFORM_STACK_SIZE 0x800
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090034#elif defined(IMAGE_BL32)
Tony Xief6118cc2016-01-15 17:17:32 +080035#define PLATFORM_STACK_SIZE 0x440
36#endif
37
38#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
39
40#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
Deepika Bhavnani73fa2d22019-12-13 10:48:54 -060041#define PLATFORM_SYSTEM_COUNT U(1)
42#define PLATFORM_CLUSTER_COUNT U(2)
43#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
44#define PLATFORM_CLUSTER1_CORE_COUNT U(2)
Tony Xief6118cc2016-01-15 17:17:32 +080045#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
46 PLATFORM_CLUSTER0_CORE_COUNT)
Deepika Bhavnani73fa2d22019-12-13 10:48:54 -060047#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
Tony Xief6118cc2016-01-15 17:17:32 +080048#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \
49 PLATFORM_CLUSTER_COUNT + \
50 PLATFORM_CORE_COUNT)
Tony Xie42e113e2016-07-16 11:16:51 +080051#define PLAT_RK_CLST_TO_CPUID_SHIFT 6
Tony Xief6118cc2016-01-15 17:17:32 +080052#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
53
54/*
55 * This macro defines the deepest retention state possible. A higher state
56 * id will represent an invalid or a power down state.
57 */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010058#define PLAT_MAX_RET_STATE U(1)
Tony Xief6118cc2016-01-15 17:17:32 +080059
60/*
61 * This macro defines the deepest power down states possible. Any state ID
62 * higher than this is invalid.
63 */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010064#define PLAT_MAX_OFF_STATE U(2)
Tony Xief6118cc2016-01-15 17:17:32 +080065
66/*******************************************************************************
Tony Xief6118cc2016-01-15 17:17:32 +080067 * Platform specific page table and MMU setup constants
68 ******************************************************************************/
Antonio Nino Diaz58230902018-09-24 17:16:20 +010069#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
70#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
Tony Xief6118cc2016-01-15 17:17:32 +080071#define MAX_XLAT_TABLES 20
Tony Xie42e113e2016-07-16 11:16:51 +080072#define MAX_MMAP_REGIONS 25
Tony Xief6118cc2016-01-15 17:17:32 +080073
74/*******************************************************************************
75 * Declarations and constants to access the mailboxes safely. Each mailbox is
76 * aligned on the biggest cache line size in the platform. This is known only
77 * to the platform as it might have a combination of integrated and external
78 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
79 * line at any cache level. They could belong to different cpus/clusters &
80 * get written while being protected by different locks causing corruption of
81 * a valid mailbox address.
82 ******************************************************************************/
83#define CACHE_WRITEBACK_SHIFT 6
84#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
85
86/*
87 * Define GICD and GICC and GICR base
88 */
89#define PLAT_RK_GICD_BASE BASE_GICD_BASE
90#define PLAT_RK_GICR_BASE BASE_GICR_BASE
91#define PLAT_RK_GICC_BASE 0
92
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080093#define PLAT_RK_UART_BASE UART2_BASE
Tony Xief6118cc2016-01-15 17:17:32 +080094#define PLAT_RK_UART_CLOCK RK3399_UART_CLOCK
95#define PLAT_RK_UART_BAUDRATE RK3399_BAUDRATE
96
97#define PLAT_RK_CCI_BASE CCI500_BASE
98
99#define PLAT_RK_PRIMARY_CPU 0x0
100
Lin Huang30e43392017-05-04 16:02:45 +0800101#define PSRAM_DO_DDR_RESUME 1
Lin Huang2a6df222017-05-12 10:26:32 +0800102#define PSRAM_CHECK_WAKEUP_CPU 0
103
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100104#endif /* PLATFORM_DEF_H */