Yann Gautier | 0775ee7 | 2021-07-02 09:35:04 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| 2 | /* |
| 3 | * Copyright (c) 2021, STMicroelectronics - All Rights Reserved |
| 4 | */ |
| 5 | |
| 6 | #include <common/tbbr/tbbr_img_def.h> |
Yann Gautier | 14afb6d | 2021-07-02 11:53:18 +0200 | [diff] [blame] | 7 | #include <dt-bindings/soc/stm32mp15-tzc400.h> |
Yann Gautier | 0775ee7 | 2021-07-02 09:35:04 +0200 | [diff] [blame] | 8 | |
| 9 | #include <platform_def.h> |
| 10 | |
Yann Gautier | 14afb6d | 2021-07-02 11:53:18 +0200 | [diff] [blame] | 11 | #ifndef DDR_SIZE |
| 12 | #error "DDR_SIZE is not defined" |
| 13 | #endif |
| 14 | |
| 15 | #define DDR_NS_BASE STM32MP_DDR_BASE |
| 16 | #ifdef AARCH32_SP_OPTEE |
| 17 | /* OP-TEE reserved shared memory: located at DDR top */ |
| 18 | #define DDR_SHARE_SIZE STM32MP_DDR_SHMEM_SIZE |
| 19 | #define DDR_SHARE_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SHARE_SIZE)) |
| 20 | /* OP-TEE secure memory: located right below OP-TEE reserved shared memory */ |
| 21 | #define DDR_SEC_SIZE STM32MP_DDR_S_SIZE |
| 22 | #define DDR_SEC_BASE (DDR_SHARE_BASE - DDR_SEC_SIZE) |
| 23 | #define DDR_NS_SIZE (DDR_SEC_BASE - DDR_NS_BASE) |
| 24 | #else /* !AARCH32_SP_OPTEE */ |
| 25 | #define DDR_NS_SIZE DDR_SIZE |
| 26 | #endif /* AARCH32_SP_OPTEE */ |
| 27 | |
Yann Gautier | 0775ee7 | 2021-07-02 09:35:04 +0200 | [diff] [blame] | 28 | /dts-v1/; |
| 29 | |
| 30 | / { |
| 31 | dtb-registry { |
| 32 | compatible = "fconf,dyn_cfg-dtb_registry"; |
| 33 | |
| 34 | hw-config { |
| 35 | load-address = <0x0 STM32MP_HW_CONFIG_BASE>; |
| 36 | max-size = <STM32MP_HW_CONFIG_MAX_SIZE>; |
| 37 | id = <HW_CONFIG_ID>; |
| 38 | }; |
| 39 | |
| 40 | nt_fw { |
| 41 | load-address = <0x0 STM32MP_BL33_BASE>; |
| 42 | max-size = <STM32MP_BL33_MAX_SIZE>; |
| 43 | id = <BL33_IMAGE_ID>; |
| 44 | }; |
| 45 | |
| 46 | #ifdef AARCH32_SP_OPTEE |
| 47 | tos_fw { |
| 48 | load-address = <0x0 STM32MP_OPTEE_BASE>; |
| 49 | max-size = <STM32MP_OPTEE_SIZE>; |
| 50 | id = <BL32_IMAGE_ID>; |
| 51 | }; |
| 52 | #else |
| 53 | tos_fw { |
| 54 | load-address = <0x0 STM32MP_BL32_BASE>; |
| 55 | max-size = <STM32MP_BL32_SIZE>; |
| 56 | id = <BL32_IMAGE_ID>; |
| 57 | }; |
| 58 | |
| 59 | tos_fw-config { |
| 60 | load-address = <0x0 STM32MP_BL32_DTB_BASE>; |
| 61 | max-size = <STM32MP_BL32_DTB_SIZE>; |
| 62 | id = <TOS_FW_CONFIG_ID>; |
| 63 | }; |
| 64 | #endif |
| 65 | }; |
Yann Gautier | 14afb6d | 2021-07-02 11:53:18 +0200 | [diff] [blame] | 66 | |
| 67 | st-mem-firewall { |
| 68 | compatible = "st,mem-firewall"; |
| 69 | #ifdef AARCH32_SP_OPTEE |
| 70 | memory-ranges = < |
| 71 | DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR |
| 72 | DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0 |
| 73 | DDR_SHARE_BASE DDR_SHARE_SIZE TZC_REGION_S_NONE |
| 74 | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID)>; |
| 75 | #else |
| 76 | memory-ranges = < |
| 77 | DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR>; |
| 78 | #endif |
| 79 | }; |
Yann Gautier | 0775ee7 | 2021-07-02 09:35:04 +0200 | [diff] [blame] | 80 | }; |