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Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Nicolas Toromanoff5a937cd2022-02-07 10:12:04 +01002 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Yann Gautier4b0c72a2018-07-16 10:54:09 +02007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <string.h>
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <arch_helpers.h>
11#include <common/debug.h>
Yann Gautiera3bd8d12021-06-18 11:33:26 +020012#include <common/desc_image_load.h>
Sughosh Ganub721f8a2021-12-01 16:45:11 +053013#include <drivers/fwu/fwu.h>
14#include <drivers/fwu/fwu_metadata.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <drivers/io/io_block.h>
16#include <drivers/io/io_driver.h>
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020017#include <drivers/io/io_fip.h>
Patrick Delaunay9c5ee782021-07-06 14:07:56 +020018#include <drivers/io/io_memmap.h>
Lionel Debieve402a46b2019-11-04 12:28:15 +010019#include <drivers/io/io_mtd.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000020#include <drivers/io/io_storage.h>
21#include <drivers/mmc.h>
Sughosh Ganub721f8a2021-12-01 16:45:11 +053022#include <drivers/partition/efi.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000023#include <drivers/partition/partition.h>
Lionel Debieve402a46b2019-11-04 12:28:15 +010024#include <drivers/raw_nand.h>
Lionel Debieve186b0462019-09-24 18:30:12 +020025#include <drivers/spi_nand.h>
Lionel Debievecb0dbc42019-09-25 09:11:31 +020026#include <drivers/spi_nor.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000027#include <drivers/st/io_mmc.h>
Lionel Debieve402a46b2019-11-04 12:28:15 +010028#include <drivers/st/stm32_fmc2_nand.h>
Lionel Debieve186b0462019-09-24 18:30:12 +020029#include <drivers/st/stm32_qspi.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000030#include <drivers/st/stm32_sdmmc2.h>
Patrick Delaunay9c5ee782021-07-06 14:07:56 +020031#include <drivers/usb_device.h>
Yann Gautier29f1f942021-07-13 18:07:41 +020032#include <lib/fconf/fconf.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000033#include <lib/mmio.h>
34#include <lib/utils.h>
35#include <plat/common/platform.h>
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020036#include <tools_share/firmware_image_package.h>
37
38#include <platform_def.h>
Patrick Delaunay9c5ee782021-07-06 14:07:56 +020039#include <stm32cubeprogrammer.h>
Yann Gautier29f1f942021-07-13 18:07:41 +020040#include <stm32mp_fconf_getter.h>
Yann Gautier8636a5f2022-05-06 15:27:32 +020041#include <stm32mp_io_storage.h>
Patrick Delaunay9c5ee782021-07-06 14:07:56 +020042#include <usb_dfu.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000043
Yann Gautier4b0c72a2018-07-16 10:54:09 +020044/* IO devices */
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020045uintptr_t fip_dev_handle;
46uintptr_t storage_dev_handle;
Yann Gautier4b0c72a2018-07-16 10:54:09 +020047
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020048static const io_dev_connector_t *fip_dev_con;
Yann Gautier8244e1d2018-10-15 09:36:58 +020049
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +020050#if STM32MP_SDMMC || STM32MP_EMMC
Yann Gautierac22dd52021-03-22 14:22:14 +010051static struct mmc_device_info mmc_info;
Yann Gautier8244e1d2018-10-15 09:36:58 +020052
Yann Gautierf9af3bc2018-11-09 15:57:18 +010053static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE);
Yann Gautier8244e1d2018-10-15 09:36:58 +020054
Yann Gautiera3bd8d12021-06-18 11:33:26 +020055static io_block_dev_spec_t mmc_block_dev_spec = {
Yann Gautier8244e1d2018-10-15 09:36:58 +020056 /* It's used as temp buffer in block driver */
57 .buffer = {
58 .offset = (size_t)&block_buffer,
59 .length = MMC_BLOCK_SIZE,
60 },
61 .ops = {
62 .read = mmc_read_blocks,
63 .write = NULL,
64 },
65 .block_size = MMC_BLOCK_SIZE,
66};
Vyacheslav Yurkove43a0802021-06-04 10:10:51 +020067
Yann Gautier8244e1d2018-10-15 09:36:58 +020068static const io_dev_connector_t *mmc_dev_con;
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +020069#endif /* STM32MP_SDMMC || STM32MP_EMMC */
Yann Gautier8244e1d2018-10-15 09:36:58 +020070
Lionel Debievecb0dbc42019-09-25 09:11:31 +020071#if STM32MP_SPI_NOR
72static io_mtd_dev_spec_t spi_nor_dev_spec = {
73 .ops = {
74 .init = spi_nor_init,
75 .read = spi_nor_read,
76 },
77};
78#endif
79
Lionel Debieve402a46b2019-11-04 12:28:15 +010080#if STM32MP_RAW_NAND
81static io_mtd_dev_spec_t nand_dev_spec = {
82 .ops = {
83 .init = nand_raw_init,
84 .read = nand_read,
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020085 .seek = nand_seek_bb
Lionel Debieve402a46b2019-11-04 12:28:15 +010086 },
87};
88
89static const io_dev_connector_t *nand_dev_con;
90#endif
91
Lionel Debieve186b0462019-09-24 18:30:12 +020092#if STM32MP_SPI_NAND
93static io_mtd_dev_spec_t spi_nand_dev_spec = {
94 .ops = {
95 .init = spi_nand_init,
96 .read = nand_read,
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020097 .seek = nand_seek_bb
Lionel Debieve186b0462019-09-24 18:30:12 +020098 },
99};
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200100#endif
Lionel Debieve186b0462019-09-24 18:30:12 +0200101
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200102#if STM32MP_SPI_NAND || STM32MP_SPI_NOR
Lionel Debieve186b0462019-09-24 18:30:12 +0200103static const io_dev_connector_t *spi_dev_con;
104#endif
105
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200106#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200107static const io_dev_connector_t *memmap_dev_con;
108#endif
109
Yann Gautier29f1f942021-07-13 18:07:41 +0200110io_block_spec_t image_block_spec = {
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200111 .offset = 0U,
112 .length = 0U,
113};
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200114
Yann Gautier29f1f942021-07-13 18:07:41 +0200115int open_fip(const uintptr_t spec)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200116{
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200117 return io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200118}
Yann Gautier8244e1d2018-10-15 09:36:58 +0200119
Yann Gautier29f1f942021-07-13 18:07:41 +0200120int open_storage(const uintptr_t spec)
Yann Gautier8244e1d2018-10-15 09:36:58 +0200121{
122 return io_dev_init(storage_dev_handle, 0);
123}
Vyacheslav Yurkove43a0802021-06-04 10:10:51 +0200124
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200125static void print_boot_device(boot_api_context_t *boot_context)
126{
127 switch (boot_context->boot_interface_selected) {
128 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
129 INFO("Using SDMMC\n");
130 break;
131 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
132 INFO("Using EMMC\n");
133 break;
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200134 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
135 INFO("Using QSPI NOR\n");
136 break;
Lionel Debieve402a46b2019-11-04 12:28:15 +0100137 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
138 INFO("Using FMC NAND\n");
139 break;
Lionel Debieve186b0462019-09-24 18:30:12 +0200140 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
141 INFO("Using SPI NAND\n");
142 break;
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200143 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
144 INFO("Using UART\n");
145 break;
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200146 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
147 INFO("Using USB\n");
148 break;
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200149 default:
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200150 ERROR("Boot interface %u not found\n",
151 boot_context->boot_interface_selected);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200152 panic();
153 break;
154 }
155
156 if (boot_context->boot_interface_instance != 0U) {
157 INFO(" Instance %d\n", boot_context->boot_interface_instance);
158 }
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200159}
160
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200161#if STM32MP_SDMMC || STM32MP_EMMC
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200162static void boot_mmc(enum mmc_device_type mmc_dev_type,
163 uint16_t boot_interface_instance)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200164{
165 int io_result __unused;
Yann Gautier8244e1d2018-10-15 09:36:58 +0200166 struct stm32_sdmmc2_params params;
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200167
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200168 zeromem(&params, sizeof(struct stm32_sdmmc2_params));
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200169
Yann Gautierac22dd52021-03-22 14:22:14 +0100170 mmc_info.mmc_dev_type = mmc_dev_type;
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200171
172 switch (boot_interface_instance) {
173 case 1:
174 params.reg_base = STM32MP_SDMMC1_BASE;
175 break;
176 case 2:
177 params.reg_base = STM32MP_SDMMC2_BASE;
178 break;
179 case 3:
180 params.reg_base = STM32MP_SDMMC3_BASE;
181 break;
182 default:
183 WARN("SDMMC instance not found, using default\n");
184 if (mmc_dev_type == MMC_IS_SD) {
185 params.reg_base = STM32MP_SDMMC1_BASE;
186 } else {
187 params.reg_base = STM32MP_SDMMC2_BASE;
188 }
189 break;
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200190 }
191
Yann Gautierac22dd52021-03-22 14:22:14 +0100192 params.device_info = &mmc_info;
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200193 if (stm32_sdmmc2_mmc_init(&params) != 0) {
194 ERROR("SDMMC%u init failed\n", boot_interface_instance);
195 panic();
196 }
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200197
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200198 /* Open MMC as a block device to read GPT table */
199 io_result = register_io_dev_block(&mmc_dev_con);
200 if (io_result != 0) {
201 panic();
202 }
Yann Gautier8244e1d2018-10-15 09:36:58 +0200203
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200204 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec,
205 &storage_dev_handle);
206 assert(io_result == 0);
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200207}
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200208#endif /* STM32MP_SDMMC || STM32MP_EMMC */
Yann Gautier8244e1d2018-10-15 09:36:58 +0200209
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200210#if STM32MP_SPI_NOR
211static void boot_spi_nor(boot_api_context_t *boot_context)
212{
213 int io_result __unused;
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200214
215 io_result = stm32_qspi_init();
216 assert(io_result == 0);
217
218 io_result = register_io_dev_mtd(&spi_dev_con);
219 assert(io_result == 0);
220
221 /* Open connections to device */
222 io_result = io_dev_open(spi_dev_con,
223 (uintptr_t)&spi_nor_dev_spec,
224 &storage_dev_handle);
225 assert(io_result == 0);
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200226}
227#endif /* STM32MP_SPI_NOR */
228
Lionel Debieve402a46b2019-11-04 12:28:15 +0100229#if STM32MP_RAW_NAND
230static void boot_fmc2_nand(boot_api_context_t *boot_context)
231{
232 int io_result __unused;
Lionel Debieve402a46b2019-11-04 12:28:15 +0100233
234 io_result = stm32_fmc2_init();
235 assert(io_result == 0);
236
237 /* Register the IO device on this platform */
238 io_result = register_io_dev_mtd(&nand_dev_con);
239 assert(io_result == 0);
240
241 /* Open connections to device */
242 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec,
243 &storage_dev_handle);
244 assert(io_result == 0);
Lionel Debieve402a46b2019-11-04 12:28:15 +0100245}
246#endif /* STM32MP_RAW_NAND */
247
Lionel Debieve186b0462019-09-24 18:30:12 +0200248#if STM32MP_SPI_NAND
249static void boot_spi_nand(boot_api_context_t *boot_context)
250{
251 int io_result __unused;
Lionel Debieve186b0462019-09-24 18:30:12 +0200252
253 io_result = stm32_qspi_init();
254 assert(io_result == 0);
255
256 io_result = register_io_dev_mtd(&spi_dev_con);
257 assert(io_result == 0);
258
259 /* Open connections to device */
260 io_result = io_dev_open(spi_dev_con,
261 (uintptr_t)&spi_nand_dev_spec,
262 &storage_dev_handle);
263 assert(io_result == 0);
Lionel Debieve186b0462019-09-24 18:30:12 +0200264}
265#endif /* STM32MP_SPI_NAND */
266
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200267#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200268static void mmap_io_setup(void)
269{
270 int io_result __unused;
271
272 io_result = register_io_dev_memmap(&memmap_dev_con);
273 assert(io_result == 0);
274
275 io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
276 &storage_dev_handle);
277 assert(io_result == 0);
278}
279
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200280#if STM32MP_UART_PROGRAMMER
281static void stm32cubeprogrammer_uart(void)
282{
283 int ret __unused;
284 boot_api_context_t *boot_context =
285 (boot_api_context_t *)stm32mp_get_boot_ctx_address();
286 uintptr_t uart_base;
287
288 uart_base = get_uart_address(boot_context->boot_interface_instance);
289 ret = stm32cubeprog_uart_load(uart_base, DWL_BUFFER_BASE, DWL_BUFFER_SIZE);
290 assert(ret == 0);
291}
292#endif
293
294#if STM32MP_USB_PROGRAMMER
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200295static void stm32cubeprogrammer_usb(void)
296{
297 int ret __unused;
298 struct usb_handle *pdev;
299
300 /* Init USB on platform */
301 pdev = usb_dfu_plat_init();
302
303 ret = stm32cubeprog_usb_load(pdev, DWL_BUFFER_BASE, DWL_BUFFER_SIZE);
304 assert(ret == 0);
305}
306#endif
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200307#endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */
308
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200309
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200310void stm32mp_io_setup(void)
311{
312 int io_result __unused;
313 boot_api_context_t *boot_context =
314 (boot_api_context_t *)stm32mp_get_boot_ctx_address();
Yann Gautierf9d40d52019-01-17 14:41:46 +0100315
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200316 print_boot_device(boot_context);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200317
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200318 if ((boot_context->boot_partition_used_toboot == 1U) ||
319 (boot_context->boot_partition_used_toboot == 2U)) {
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200320 INFO("Boot used partition fsbl%u\n",
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200321 boot_context->boot_partition_used_toboot);
322 }
Yann Gautier8244e1d2018-10-15 09:36:58 +0200323
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200324 io_result = register_io_dev_fip(&fip_dev_con);
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200325 assert(io_result == 0);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200326
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200327 io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
328 &fip_dev_handle);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200329
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200330 switch (boot_context->boot_interface_selected) {
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200331#if STM32MP_SDMMC
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200332 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
333 dmbsy();
334 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance);
335 break;
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200336#endif
337#if STM32MP_EMMC
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200338 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
339 dmbsy();
340 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200341 break;
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200342#endif
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200343#if STM32MP_SPI_NOR
344 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
345 dmbsy();
346 boot_spi_nor(boot_context);
347 break;
348#endif
Lionel Debieve402a46b2019-11-04 12:28:15 +0100349#if STM32MP_RAW_NAND
350 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
351 dmbsy();
352 boot_fmc2_nand(boot_context);
353 break;
354#endif
Lionel Debieve186b0462019-09-24 18:30:12 +0200355#if STM32MP_SPI_NAND
356 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
357 dmbsy();
358 boot_spi_nand(boot_context);
359 break;
360#endif
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200361#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
362#if STM32MP_UART_PROGRAMMER
363 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
364#endif
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200365#if STM32MP_USB_PROGRAMMER
366 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200367#endif
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200368 dmbsy();
369 mmap_io_setup();
370 break;
371#endif
Yann Gautier8244e1d2018-10-15 09:36:58 +0200372
373 default:
374 ERROR("Boot interface %d not supported\n",
375 boot_context->boot_interface_selected);
Yann Gautier4c2b73d2021-06-30 17:04:22 +0200376 panic();
Yann Gautier8244e1d2018-10-15 09:36:58 +0200377 break;
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200378 }
379}
380
381int bl2_plat_handle_pre_image_load(unsigned int image_id)
382{
383 static bool gpt_init_done __unused;
384 uint16_t boot_itf = stm32mp_get_boot_itf_selected();
385
386 switch (boot_itf) {
387#if STM32MP_SDMMC || STM32MP_EMMC
388 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
389 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
390 if (!gpt_init_done) {
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530391/*
392 * With FWU Multi Bank feature enabled, the selection of
393 * the image to boot will be done by fwu_init calling the
394 * platform hook, plat_fwu_set_images_source.
395 */
396#if !PSA_FWU_SUPPORT
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200397 const partition_entry_t *entry;
398
399 partition_init(GPT_IMAGE_ID);
400 entry = get_partition_entry(FIP_IMAGE_NAME);
401 if (entry == NULL) {
402 ERROR("Could NOT find the %s partition!\n",
403 FIP_IMAGE_NAME);
404 return -ENOENT;
405 }
406
407 image_block_spec.offset = entry->start;
408 image_block_spec.length = entry->length;
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530409#endif
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200410 gpt_init_done = true;
Yann Gautiera3bd8d12021-06-18 11:33:26 +0200411 } else {
412 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Yann Gautierc6f77b02022-05-06 09:50:43 +0200413 assert(bl_mem_params != NULL);
Yann Gautiera3bd8d12021-06-18 11:33:26 +0200414
415 mmc_block_dev_spec.buffer.offset = bl_mem_params->image_info.image_base;
416 mmc_block_dev_spec.buffer.length = bl_mem_params->image_info.image_max_size;
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200417 }
418
419 break;
420#endif
421
422#if STM32MP_RAW_NAND || STM32MP_SPI_NAND
423#if STM32MP_RAW_NAND
424 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
425#endif
426#if STM32MP_SPI_NAND
427 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
428#endif
429 image_block_spec.offset = STM32MP_NAND_FIP_OFFSET;
430 break;
431#endif
432
433#if STM32MP_SPI_NOR
434 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
435 image_block_spec.offset = STM32MP_NOR_FIP_OFFSET;
436 break;
437#endif
438
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200439#if STM32MP_UART_PROGRAMMER
440 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
441 if (image_id == FW_CONFIG_ID) {
442 stm32cubeprogrammer_uart();
443 /* FIP loaded at DWL address */
444 image_block_spec.offset = DWL_BUFFER_BASE;
445 image_block_spec.length = DWL_BUFFER_SIZE;
446 }
447 break;
448#endif
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200449#if STM32MP_USB_PROGRAMMER
450 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
451 if (image_id == FW_CONFIG_ID) {
452 stm32cubeprogrammer_usb();
453 /* FIP loaded at DWL address */
454 image_block_spec.offset = DWL_BUFFER_BASE;
455 image_block_spec.length = DWL_BUFFER_SIZE;
456 }
457 break;
458#endif
459
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200460 default:
461 ERROR("FIP Not found\n");
462 panic();
Yann Gautier8244e1d2018-10-15 09:36:58 +0200463 }
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200464
465 return 0;
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200466}
467
468/*
469 * Return an IO device handle and specification which can be used to access
470 * an image. Use this to enforce platform load policy.
471 */
472int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
473 uintptr_t *image_spec)
474{
475 int rc;
476 const struct plat_io_policy *policy;
477
Yann Gautier29f1f942021-07-13 18:07:41 +0200478 policy = FCONF_GET_PROPERTY(stm32mp, io_policies, image_id);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200479 rc = policy->check(policy->image_spec);
480 if (rc == 0) {
481 *image_spec = policy->image_spec;
482 *dev_handle = *(policy->dev_handle);
483 }
484
485 return rc;
486}
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530487
488#if (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT
489/*
Nicolas Toromanoff5a937cd2022-02-07 10:12:04 +0100490 * In each boot in non-trial mode, we set the BKP register to
491 * FWU_MAX_TRIAL_REBOOT, and return the active_index from metadata.
492 *
493 * As long as the update agent didn't update the "accepted" field in metadata
494 * (i.e. we are in trial mode), we select the new active_index.
495 * To avoid infinite boot loop at trial boot we decrement a BKP register.
496 * If this counter is 0:
497 * - an unexpected TAMPER event raised (that resets the BKP registers to 0)
498 * - a power-off occurs before the update agent was able to update the
499 * "accepted' field
500 * - we already boot FWU_MAX_TRIAL_REBOOT times in trial mode.
501 * we select the previous_active_index.
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530502 */
Nicolas Toromanoff5a937cd2022-02-07 10:12:04 +0100503#define INVALID_BOOT_IDX 0xFFFFFFFF
504
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530505uint32_t plat_fwu_get_boot_idx(void)
506{
Nicolas Toromanoff5a937cd2022-02-07 10:12:04 +0100507 /*
508 * Select boot index and update boot counter only once per boot
509 * even if this function is called several times.
510 */
511 static uint32_t boot_idx = INVALID_BOOT_IDX;
512 const struct fwu_metadata *data;
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530513
Nicolas Toromanoff5a937cd2022-02-07 10:12:04 +0100514 data = fwu_get_metadata();
515
516 if (boot_idx == INVALID_BOOT_IDX) {
517 boot_idx = data->active_index;
518 if (fwu_is_trial_run_state()) {
519 if (stm32_get_and_dec_fwu_trial_boot_cnt() == 0U) {
520 WARN("Trial FWU fails %u times\n",
521 FWU_MAX_TRIAL_REBOOT);
522 boot_idx = data->previous_active_index;
523 }
524 } else {
525 stm32_set_max_fwu_trial_boot_cnt();
526 }
527 }
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530528
Nicolas Toromanoff5a937cd2022-02-07 10:12:04 +0100529 return boot_idx;
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530530}
531
532static void *stm32_get_image_spec(const uuid_t *img_type_uuid)
533{
534 unsigned int i;
535
536 for (i = 0U; i < MAX_NUMBER_IDS; i++) {
537 if ((guidcmp(&policies[i].img_type_guid, img_type_uuid)) == 0) {
538 return (void *)policies[i].image_spec;
539 }
540 }
541
542 return NULL;
543}
544
545void plat_fwu_set_images_source(const struct fwu_metadata *metadata)
546{
547 unsigned int i;
548 uint32_t boot_idx;
549 const partition_entry_t *entry;
550 const uuid_t *img_type_uuid, *img_uuid;
551 io_block_spec_t *image_spec;
552
553 boot_idx = plat_fwu_get_boot_idx();
554 assert(boot_idx < NR_OF_FW_BANKS);
555
556 for (i = 0U; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
557 img_type_uuid = &metadata->img_entry[i].img_type_uuid;
558 image_spec = stm32_get_image_spec(img_type_uuid);
559 if (image_spec == NULL) {
560 ERROR("Unable to get image spec for the image in the metadata\n");
561 panic();
562 }
563
564 img_uuid =
565 &metadata->img_entry[i].img_props[boot_idx].img_uuid;
566
567 entry = get_partition_entry_by_uuid(img_uuid);
568 if (entry == NULL) {
569 ERROR("Unable to find the partition with the uuid mentioned in metadata\n");
570 panic();
571 }
572
573 image_spec->offset = entry->start;
574 image_spec->length = entry->length;
575 }
576}
Sughosh Ganud1f87132021-12-01 16:46:34 +0530577
578static int plat_set_image_source(unsigned int image_id,
579 uintptr_t *handle,
580 uintptr_t *image_spec,
581 const char *part_name)
582{
583 struct plat_io_policy *policy;
584 io_block_spec_t *spec;
585 const partition_entry_t *entry = get_partition_entry(part_name);
586
587 if (entry == NULL) {
588 ERROR("Unable to find the %s partition\n", part_name);
589 return -ENOENT;
590 }
591
592 policy = &policies[image_id];
593
594 spec = (io_block_spec_t *)policy->image_spec;
595 spec->offset = entry->start;
596 spec->length = entry->length;
597
598 *image_spec = policy->image_spec;
599 *handle = *policy->dev_handle;
600
601 return 0;
602}
603
604int plat_fwu_set_metadata_image_source(unsigned int image_id,
605 uintptr_t *handle,
606 uintptr_t *image_spec)
607{
608 char *part_name;
609
610 assert((image_id == FWU_METADATA_IMAGE_ID) ||
611 (image_id == BKUP_FWU_METADATA_IMAGE_ID));
612
613 partition_init(GPT_IMAGE_ID);
614
615 if (image_id == FWU_METADATA_IMAGE_ID) {
616 part_name = METADATA_PART_1;
617 } else {
618 part_name = METADATA_PART_2;
619 }
620
621 return plat_set_image_source(image_id, handle, image_spec,
622 part_name);
623}
Sughosh Ganub721f8a2021-12-01 16:45:11 +0530624#endif /* (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT */