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developer2189d3a2020-04-17 17:14:23 +08001/*
2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
10
11#define PLAT_PRIMARY_CPU 0x0
12
13#define MT_GIC_BASE 0x0c000000
14#define PLAT_MT_CCI_BASE 0x0c500000
15#define MCUCFG_BASE 0x0c530000
16
17#define IO_PHYS 0x10000000
18
19/* Aggregate of all devices for MMU mapping */
20#define MTK_DEV_RNG0_BASE IO_PHYS
21#define MTK_DEV_RNG0_SIZE 0x10000000
22#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x10000000)
23#define MTK_DEV_RNG1_SIZE 0x10000000
24#define MTK_DEV_RNG2_BASE 0x0c000000
25#define MTK_DEV_RNG2_SIZE 0x600000
developera444a202020-06-15 16:41:03 +080026#define MTK_MCDI_SRAM_BASE 0x11B000
27#define MTK_MCDI_SRAM_MAP_SIZE 0x1000
developer2189d3a2020-04-17 17:14:23 +080028
developer0df1c3c2020-08-01 16:23:12 +080029#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
developer404e08b2020-09-18 09:32:31 +080030#define GPIO_BASE (IO_PHYS + 0x00005000)
developer31f56a72020-06-16 13:28:28 +080031#define SPM_BASE (IO_PHYS + 0x00006000)
developer74cf3ec2020-08-12 16:31:06 +080032#define PMIC_WRAP_BASE (IO_PHYS + 0x00026000)
developer404e08b2020-09-18 09:32:31 +080033#define IOCFG_RM_BASE (IO_PHYS + 0x01C20000)
34#define IOCFG_BM_BASE (IO_PHYS + 0x01D10000)
35#define IOCFG_BL_BASE (IO_PHYS + 0x01D30000)
36#define IOCFG_BR_BASE (IO_PHYS + 0x01D40000)
37#define IOCFG_LM_BASE (IO_PHYS + 0x01E20000)
38#define IOCFG_LB_BASE (IO_PHYS + 0x01E70000)
39#define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000)
40#define IOCFG_LT_BASE (IO_PHYS + 0x01F20000)
41#define IOCFG_TL_BASE (IO_PHYS + 0x01F30000)
developer2189d3a2020-04-17 17:14:23 +080042/*******************************************************************************
43 * UART related constants
44 ******************************************************************************/
45#define UART0_BASE (IO_PHYS + 0x01002000)
46#define UART1_BASE (IO_PHYS + 0x01003000)
47
48#define UART_BAUDRATE 115200
49
50/*******************************************************************************
51 * System counter frequency related constants
52 ******************************************************************************/
53#define SYS_COUNTER_FREQ_IN_TICKS 13000000
54#define SYS_COUNTER_FREQ_IN_MHZ 13
55
56/*******************************************************************************
developerf9b56842020-06-09 13:38:35 +080057 * GIC-400 & interrupt handling related constants
58 ******************************************************************************/
59
60/* Base MTK_platform compatible GIC memory map */
61#define BASE_GICD_BASE MT_GIC_BASE
62#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
63
64/*******************************************************************************
developer2189d3a2020-04-17 17:14:23 +080065 * Platform binary types for linking
66 ******************************************************************************/
67#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
68#define PLATFORM_LINKER_ARCH aarch64
69
70/*******************************************************************************
71 * Generic platform constants
72 ******************************************************************************/
73#define PLATFORM_STACK_SIZE 0x800
74
developer0b0c04d2020-06-16 11:48:36 +080075#define PLAT_MAX_PWR_LVL U(3)
developer2189d3a2020-04-17 17:14:23 +080076#define PLAT_MAX_RET_STATE U(1)
developer0b0c04d2020-06-16 11:48:36 +080077#define PLAT_MAX_OFF_STATE U(9)
developer2189d3a2020-04-17 17:14:23 +080078
79#define PLATFORM_SYSTEM_COUNT U(1)
developer0b0c04d2020-06-16 11:48:36 +080080#define PLATFORM_MCUSYS_COUNT U(1)
developer2189d3a2020-04-17 17:14:23 +080081#define PLATFORM_CLUSTER_COUNT U(1)
82#define PLATFORM_CLUSTER0_CORE_COUNT U(8)
83#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
84#define PLATFORM_MAX_CPUS_PER_CLUSTER U(8)
85
Hsin-Yi Wange0bf3052020-08-27 13:48:48 +080086#define SOC_CHIP_ID U(0x8192)
87
developer2189d3a2020-04-17 17:14:23 +080088/*******************************************************************************
89 * Platform memory map related constants
90 ******************************************************************************/
91#define TZRAM_BASE 0x54600000
92#define TZRAM_SIZE 0x00030000
93
94/*******************************************************************************
95 * BL31 specific defines.
96 ******************************************************************************/
97/*
98 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
99 * present). BL31_BASE is calculated using the current BL31 debug size plus a
100 * little space for growth.
101 */
102#define BL31_BASE (TZRAM_BASE + 0x1000)
103#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
104
105/*******************************************************************************
106 * Platform specific page table and MMU setup constants
107 ******************************************************************************/
108#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
109#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
110#define MAX_XLAT_TABLES 16
111#define MAX_MMAP_REGIONS 16
112
113/*******************************************************************************
114 * Declarations and constants to access the mailboxes safely. Each mailbox is
115 * aligned on the biggest cache line size in the platform. This is known only
116 * to the platform as it might have a combination of integrated and external
117 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
118 * line at any cache level. They could belong to different cpus/clusters &
119 * get written while being protected by different locks causing corruption of
120 * a valid mailbox address.
121 ******************************************************************************/
122#define CACHE_WRITEBACK_SHIFT 6
123#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
124#endif /* PLATFORM_DEF_H */