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Soby Mathewec8ac1c2016-05-05 14:32:05 +01001/*
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +00002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Soby Mathewec8ac1c2016-05-05 14:32:05 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewec8ac1c2016-05-05 14:32:05 +01005 */
6
7#include <arch.h>
8#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <common/bl_common.h>
10#include <common/runtime_svc.h>
Soby Mathewec8ac1c2016-05-05 14:32:05 +010011#include <context.h>
Yatharth Kochar06460cd2016-06-30 15:02:31 +010012#include <el3_common_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <lib/xlat_tables/xlat_tables_defs.h>
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +000014#include <smccc_helpers.h>
15#include <smccc_macros.S>
Soby Mathewec8ac1c2016-05-05 14:32:05 +010016
17 .globl sp_min_vector_table
18 .globl sp_min_entrypoint
19 .globl sp_min_warm_entrypoint
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +000020 .globl sp_min_handle_smc
21 .globl sp_min_handle_fiq
Soby Mathewec8ac1c2016-05-05 14:32:05 +010022
Etienne Carrieredc0fea72017-08-09 15:48:53 +020023 .macro route_fiq_to_sp_min reg
24 /* -----------------------------------------------------
25 * FIQs are secure interrupts trapped by Monitor and non
26 * secure is not allowed to mask the FIQs.
27 * -----------------------------------------------------
28 */
29 ldcopr \reg, SCR
30 orr \reg, \reg, #SCR_FIQ_BIT
31 bic \reg, \reg, #SCR_FW_BIT
32 stcopr \reg, SCR
33 .endm
Yatharth Kochar06460cd2016-06-30 15:02:31 +010034
Etienne Carriere7555ab72017-11-08 13:49:12 +010035 .macro clrex_on_monitor_entry
36#if (ARM_ARCH_MAJOR == 7)
37 /*
38 * ARMv7 architectures need to clear the exclusive access when
39 * entering Monitor mode.
40 */
41 clrex
42#endif
43 .endm
44
Yatharth Kochar06460cd2016-06-30 15:02:31 +010045vector_base sp_min_vector_table
Soby Mathewec8ac1c2016-05-05 14:32:05 +010046 b sp_min_entrypoint
47 b plat_panic_handler /* Undef */
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +000048 b sp_min_handle_smc /* Syscall */
Soby Mathewec8ac1c2016-05-05 14:32:05 +010049 b plat_panic_handler /* Prefetch abort */
50 b plat_panic_handler /* Data abort */
51 b plat_panic_handler /* Reserved */
52 b plat_panic_handler /* IRQ */
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +000053 b sp_min_handle_fiq /* FIQ */
Soby Mathewec8ac1c2016-05-05 14:32:05 +010054
Soby Mathewec8ac1c2016-05-05 14:32:05 +010055
56/*
57 * The Cold boot/Reset entrypoint for SP_MIN
58 */
59func sp_min_entrypoint
Yatharth Kochar06460cd2016-06-30 15:02:31 +010060#if !RESET_TO_SP_MIN
61 /* ---------------------------------------------------------------
62 * Preceding bootloader has populated r0 with a pointer to a
63 * 'bl_params_t' structure & r1 with a pointer to platform
64 * specific structure
65 * ---------------------------------------------------------------
Soby Mathewec8ac1c2016-05-05 14:32:05 +010066 */
Soby Mathew73308d02018-01-09 14:36:14 +000067 mov r9, r0
68 mov r10, r1
69 mov r11, r2
70 mov r12, r3
Soby Mathewec8ac1c2016-05-05 14:32:05 +010071
Yatharth Kochar06460cd2016-06-30 15:02:31 +010072 /* ---------------------------------------------------------------------
73 * For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches
74 * sp_min_entrypoint() during the cold boot flow, so the cold/warm boot
75 * and primary/secondary CPU logic should not be executed in this case.
76 *
David Cunadofee86532017-04-13 22:38:29 +010077 * Also, assume that the previous bootloader has already initialised the
78 * SCTLR, including the CPU endianness, and has initialised the memory.
Yatharth Kochar06460cd2016-06-30 15:02:31 +010079 * ---------------------------------------------------------------------
Soby Mathewec8ac1c2016-05-05 14:32:05 +010080 */
Yatharth Kochar06460cd2016-06-30 15:02:31 +010081 el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +010082 _init_sctlr=0 \
Yatharth Kochar06460cd2016-06-30 15:02:31 +010083 _warm_boot_mailbox=0 \
84 _secondary_cold_boot=0 \
85 _init_memory=0 \
86 _init_c_runtime=1 \
87 _exception_vectors=sp_min_vector_table
Soby Mathewec8ac1c2016-05-05 14:32:05 +010088
Yatharth Kochar06460cd2016-06-30 15:02:31 +010089 /* ---------------------------------------------------------------------
90 * Relay the previous bootloader's arguments to the platform layer
91 * ---------------------------------------------------------------------
Soby Mathewec8ac1c2016-05-05 14:32:05 +010092 */
Yatharth Kochar06460cd2016-06-30 15:02:31 +010093#else
94 /* ---------------------------------------------------------------------
95 * For RESET_TO_SP_MIN systems which have a programmable reset address,
96 * sp_min_entrypoint() is executed only on the cold boot path so we can
97 * skip the warm boot mailbox mechanism.
98 * ---------------------------------------------------------------------
Soby Mathewec8ac1c2016-05-05 14:32:05 +010099 */
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100100 el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +0100101 _init_sctlr=1 \
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100102 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
103 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
104 _init_memory=1 \
105 _init_c_runtime=1 \
106 _exception_vectors=sp_min_vector_table
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100107
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100108 /* ---------------------------------------------------------------------
109 * For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader
110 * to run so there's no argument to relay from a previous bootloader.
111 * Zero the arguments passed to the platform layer to reflect that.
112 * ---------------------------------------------------------------------
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100113 */
Soby Mathew73308d02018-01-09 14:36:14 +0000114 mov r9, #0
115 mov r10, #0
116 mov r11, #0
117 mov r12, #0
118
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100119#endif /* RESET_TO_SP_MIN */
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100120
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200121#if SP_MIN_WITH_SECURE_FIQ
122 route_fiq_to_sp_min r4
123#endif
124
Soby Mathew73308d02018-01-09 14:36:14 +0000125 mov r0, r9
126 mov r1, r10
127 mov r2, r11
128 mov r3, r12
129 bl sp_min_early_platform_setup2
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100130 bl sp_min_plat_arch_setup
131
132 /* Jump to the main function */
133 bl sp_min_main
134
135 /* -------------------------------------------------------------
136 * Clean the .data & .bss sections to main memory. This ensures
137 * that any global data which was initialised by the primary CPU
138 * is visible to secondary CPUs before they enable their data
139 * caches and participate in coherency.
140 * -------------------------------------------------------------
141 */
142 ldr r0, =__DATA_START__
143 ldr r1, =__DATA_END__
144 sub r1, r1, r0
145 bl clean_dcache_range
146
147 ldr r0, =__BSS_START__
148 ldr r1, =__BSS_END__
149 sub r1, r1, r0
150 bl clean_dcache_range
151
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100152 bl smc_get_next_ctx
Soby Mathewf3e3a432017-03-30 14:42:54 +0100153
154 /* r0 points to `smc_ctx_t` */
155 /* The PSCI cpu_context registers have been copied to `smc_ctx_t` */
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100156 b sp_min_exit
157endfunc sp_min_entrypoint
158
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100159
160/*
161 * SMC handling function for SP_MIN.
162 */
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +0000163func sp_min_handle_smc
Soby Mathewf3e3a432017-03-30 14:42:54 +0100164 /* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
165 str lr, [sp, #SMC_CTX_LR_MON]
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100166
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +0000167 smccc_save_gp_mode_regs
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100168
Etienne Carriere7555ab72017-11-08 13:49:12 +0100169 clrex_on_monitor_entry
170
Soby Mathewadb70272016-12-06 12:10:51 +0000171 /*
Soby Mathewf3e3a432017-03-30 14:42:54 +0100172 * `sp` still points to `smc_ctx_t`. Save it to a register
173 * and restore the C runtime stack pointer to `sp`.
Soby Mathewadb70272016-12-06 12:10:51 +0000174 */
Soby Mathewf3e3a432017-03-30 14:42:54 +0100175 mov r2, sp /* handle */
176 ldr sp, [r2, #SMC_CTX_SP_MON]
177
178 ldr r0, [r2, #SMC_CTX_SCR]
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100179 and r3, r0, #SCR_NS_BIT /* flags */
180
181 /* Switch to Secure Mode*/
182 bic r0, #SCR_NS_BIT
183 stcopr r0, SCR
184 isb
Soby Mathewf3e3a432017-03-30 14:42:54 +0100185
David Cunado4168f2f2017-10-02 17:41:39 +0100186 /*
187 * Set PMCR.DP to 1 to prohibit cycle counting whilst in Secure Mode.
188 * Also, the PMCR.LC field has an architecturally UNKNOWN value on reset
189 * and so set to 1 as ARM has deprecated use of PMCR.LC=0.
190 */
191 ldcopr r0, PMCR
192 orr r0, r0, #(PMCR_LC_BIT | PMCR_DP_BIT)
193 stcopr r0, PMCR
194
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100195 ldr r0, [r2, #SMC_CTX_GPREG_R0] /* smc_fid */
196 /* Check whether an SMC64 is issued */
197 tst r0, #(FUNCID_CC_MASK << FUNCID_CC_SHIFT)
Soby Mathewf3e3a432017-03-30 14:42:54 +0100198 beq 1f
199 /* SMC32 is not detected. Return error back to caller */
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100200 mov r0, #SMC_UNK
201 str r0, [r2, #SMC_CTX_GPREG_R0]
202 mov r0, r2
Soby Mathewf3e3a432017-03-30 14:42:54 +0100203 b sp_min_exit
Yatharth Kochar06460cd2016-06-30 15:02:31 +01002041:
Soby Mathewf3e3a432017-03-30 14:42:54 +0100205 /* SMC32 is detected */
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100206 mov r1, #0 /* cookie */
207 bl handle_runtime_svc
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100208
Soby Mathewf3e3a432017-03-30 14:42:54 +0100209 /* `r0` points to `smc_ctx_t` */
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100210 b sp_min_exit
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +0000211endfunc sp_min_handle_smc
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100212
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100213/*
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200214 * Secure Interrupts handling function for SP_MIN.
215 */
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +0000216func sp_min_handle_fiq
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200217#if !SP_MIN_WITH_SECURE_FIQ
218 b plat_panic_handler
219#else
220 /* FIQ has a +4 offset for lr compared to preferred return address */
221 sub lr, lr, #4
222 /* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
223 str lr, [sp, #SMC_CTX_LR_MON]
224
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +0000225 smccc_save_gp_mode_regs
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200226
Etienne Carriere7555ab72017-11-08 13:49:12 +0100227 clrex_on_monitor_entry
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200228
229 /* load run-time stack */
230 mov r2, sp
231 ldr sp, [r2, #SMC_CTX_SP_MON]
232
233 /* Switch to Secure Mode */
234 ldr r0, [r2, #SMC_CTX_SCR]
235 bic r0, #SCR_NS_BIT
236 stcopr r0, SCR
237 isb
238
David Cunado4168f2f2017-10-02 17:41:39 +0100239 /*
240 * Set PMCR.DP to 1 to prohibit cycle counting whilst in Secure Mode.
241 * Also, the PMCR.LC field has an architecturally UNKNOWN value on reset
242 * and so set to 1 as ARM has deprecated use of PMCR.LC=0.
243 */
244 ldcopr r0, PMCR
245 orr r0, r0, #(PMCR_LC_BIT | PMCR_DP_BIT)
246 stcopr r0, PMCR
247
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200248 push {r2, r3}
249 bl sp_min_fiq
250 pop {r0, r3}
251
252 b sp_min_exit
253#endif
Dimitris Papastamos0a4cded2018-01-02 11:37:02 +0000254endfunc sp_min_handle_fiq
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200255
256/*
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100257 * The Warm boot entrypoint for SP_MIN.
258 */
259func sp_min_warm_entrypoint
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100260 /*
261 * On the warm boot path, most of the EL3 initialisations performed by
262 * 'el3_entrypoint_common' must be skipped:
263 *
264 * - Only when the platform bypasses the BL1/BL32 (SP_MIN) entrypoint by
David Cunadofee86532017-04-13 22:38:29 +0100265 * programming the reset address do we need to initialied the SCTLR.
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100266 * In other cases, we assume this has been taken care by the
267 * entrypoint code.
268 *
269 * - No need to determine the type of boot, we know it is a warm boot.
270 *
271 * - Do not try to distinguish between primary and secondary CPUs, this
272 * notion only exists for a cold boot.
273 *
274 * - No need to initialise the memory or the C runtime environment,
275 * it has been done once and for all on the cold boot path.
276 */
277 el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +0100278 _init_sctlr=PROGRAMMABLE_RESET_ADDRESS \
Yatharth Kochar06460cd2016-06-30 15:02:31 +0100279 _warm_boot_mailbox=0 \
280 _secondary_cold_boot=0 \
281 _init_memory=0 \
282 _init_c_runtime=0 \
283 _exception_vectors=sp_min_vector_table
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100284
Jeenu Viswambharan46144962017-01-05 10:37:21 +0000285 /*
286 * We're about to enable MMU and participate in PSCI state coordination.
287 *
288 * The PSCI implementation invokes platform routines that enable CPUs to
289 * participate in coherency. On a system where CPUs are not
Soby Mathew043fe9c2017-04-10 22:35:42 +0100290 * cache-coherent without appropriate platform specific programming,
291 * having caches enabled until such time might lead to coherency issues
292 * (resulting from stale data getting speculatively fetched, among
293 * others). Therefore we keep data caches disabled even after enabling
294 * the MMU for such platforms.
Jeenu Viswambharan46144962017-01-05 10:37:21 +0000295 *
Soby Mathew043fe9c2017-04-10 22:35:42 +0100296 * On systems with hardware-assisted coherency, or on single cluster
297 * platforms, such platform specific programming is not required to
298 * enter coherency (as CPUs already are); and there's no reason to have
299 * caches disabled either.
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100300 */
Jeenu Viswambharane834ee12018-04-27 15:17:03 +0100301#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
302 mov r0, #0
303#else
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100304 mov r0, #DISABLE_DCACHE
Jeenu Viswambharane834ee12018-04-27 15:17:03 +0100305#endif
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100306 bl bl32_plat_enable_mmu
307
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200308#if SP_MIN_WITH_SECURE_FIQ
309 route_fiq_to_sp_min r0
310#endif
311
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100312 bl sp_min_warm_boot
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100313 bl smc_get_next_ctx
Soby Mathewf3e3a432017-03-30 14:42:54 +0100314 /* r0 points to `smc_ctx_t` */
315 /* The PSCI cpu_context registers have been copied to `smc_ctx_t` */
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100316 b sp_min_exit
317endfunc sp_min_warm_entrypoint
318
319/*
320 * The function to restore the registers from SMC context and return
321 * to the mode restored to SPSR.
322 *
323 * Arguments : r0 must point to the SMC context to restore from.
324 */
325func sp_min_exit
Soby Mathewf3e3a432017-03-30 14:42:54 +0100326 monitor_exit
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100327endfunc sp_min_exit