Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <string.h> |
| 32 | #include <assert.h> |
| 33 | #include <arch.h> |
| 34 | |
| 35 | /******************************************************************************* |
| 36 | * Helper to create a level 1/2 table descriptor which points to a level 2/3 |
| 37 | * table. |
| 38 | ******************************************************************************/ |
| 39 | unsigned long create_table_desc(unsigned long *next_table_ptr) |
| 40 | { |
| 41 | unsigned long desc = (unsigned long) next_table_ptr; |
| 42 | |
| 43 | /* Clear the last 12 bits */ |
| 44 | desc >>= FOUR_KB_SHIFT; |
| 45 | desc <<= FOUR_KB_SHIFT; |
| 46 | |
| 47 | desc |= TABLE_DESC; |
| 48 | |
| 49 | return desc; |
| 50 | } |
| 51 | |
| 52 | /******************************************************************************* |
| 53 | * Helper to create a level 1/2/3 block descriptor which maps the va to addr |
| 54 | ******************************************************************************/ |
| 55 | unsigned long create_block_desc(unsigned long desc, |
| 56 | unsigned long addr, |
| 57 | unsigned int level) |
| 58 | { |
| 59 | switch (level) { |
| 60 | case LEVEL1: |
| 61 | desc |= (addr << FIRST_LEVEL_DESC_N) | BLOCK_DESC; |
| 62 | break; |
| 63 | case LEVEL2: |
| 64 | desc |= (addr << SECOND_LEVEL_DESC_N) | BLOCK_DESC; |
| 65 | break; |
| 66 | case LEVEL3: |
| 67 | desc |= (addr << THIRD_LEVEL_DESC_N) | TABLE_DESC; |
| 68 | break; |
| 69 | default: |
| 70 | assert(0); |
| 71 | } |
| 72 | |
| 73 | return desc; |
| 74 | } |
| 75 | |
| 76 | /******************************************************************************* |
| 77 | * Helper to create a level 1/2/3 block descriptor which maps the va to output_ |
| 78 | * addr with Device nGnRE attributes. |
| 79 | ******************************************************************************/ |
| 80 | unsigned long create_device_block(unsigned long output_addr, |
| 81 | unsigned int level, |
| 82 | unsigned int ns) |
| 83 | { |
| 84 | unsigned long upper_attrs, lower_attrs, desc; |
| 85 | |
| 86 | lower_attrs = LOWER_ATTRS(ACCESS_FLAG | OSH | AP_RW); |
| 87 | lower_attrs |= LOWER_ATTRS(ns | ATTR_DEVICE_INDEX); |
| 88 | upper_attrs = UPPER_ATTRS(XN); |
| 89 | desc = upper_attrs | lower_attrs; |
| 90 | |
| 91 | return create_block_desc(desc, output_addr, level); |
| 92 | } |
| 93 | |
| 94 | /******************************************************************************* |
| 95 | * Helper to create a level 1/2/3 block descriptor which maps the va to output_ |
| 96 | * addr with inner-shareable normal wbwa read-only memory attributes. |
| 97 | ******************************************************************************/ |
| 98 | unsigned long create_romem_block(unsigned long output_addr, |
| 99 | unsigned int level, |
| 100 | unsigned int ns) |
| 101 | { |
| 102 | unsigned long upper_attrs, lower_attrs, desc; |
| 103 | |
| 104 | lower_attrs = LOWER_ATTRS(ACCESS_FLAG | ISH | AP_RO); |
| 105 | lower_attrs |= LOWER_ATTRS(ns | ATTR_IWBWA_OWBWA_NTR_INDEX); |
| 106 | upper_attrs = UPPER_ATTRS(0ull); |
| 107 | desc = upper_attrs | lower_attrs; |
| 108 | |
| 109 | return create_block_desc(desc, output_addr, level); |
| 110 | } |
| 111 | |
| 112 | /******************************************************************************* |
| 113 | * Helper to create a level 1/2/3 block descriptor which maps the va to output_ |
| 114 | * addr with inner-shareable normal wbwa read-write memory attributes. |
| 115 | ******************************************************************************/ |
| 116 | unsigned long create_rwmem_block(unsigned long output_addr, |
| 117 | unsigned int level, |
| 118 | unsigned int ns) |
| 119 | { |
| 120 | unsigned long upper_attrs, lower_attrs, desc; |
| 121 | |
| 122 | lower_attrs = LOWER_ATTRS(ACCESS_FLAG | ISH | AP_RW); |
| 123 | lower_attrs |= LOWER_ATTRS(ns | ATTR_IWBWA_OWBWA_NTR_INDEX); |
| 124 | upper_attrs = UPPER_ATTRS(XN); |
| 125 | desc = upper_attrs | lower_attrs; |
| 126 | |
| 127 | return create_block_desc(desc, output_addr, level); |
| 128 | } |