| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __PLATFORM_DEF_H__ |
| 32 | #define __PLATFORM_DEF_H__ |
| 33 | |
| 34 | #include <arch.h> |
| 35 | #include <common_def.h> |
| 36 | |
| 37 | /******************************************************************************* |
| 38 | * Generic platform constants |
| 39 | ******************************************************************************/ |
| 40 | |
| 41 | /* Size of cacheable stacks */ |
| 42 | #if DEBUG_XLAT_TABLE |
| 43 | #define PLATFORM_STACK_SIZE 0x800 |
| 44 | #elif IMAGE_BL31 |
| 45 | #define PLATFORM_STACK_SIZE 0x400 |
| 46 | #endif |
| 47 | |
| 48 | #define TEGRA_PRIMARY_CPU 0x0 |
| 49 | |
| 50 | #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 |
| 51 | #define PLATFORM_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER |
| 52 | #define PLATFORM_NUM_AFFS ((PLATFORM_CLUSTER_COUNT * \ |
| 53 | PLATFORM_CORE_COUNT) + \ |
| 54 | PLATFORM_CLUSTER_COUNT + 1) |
| 55 | |
| 56 | /******************************************************************************* |
| 57 | * Platform console related constants |
| 58 | ******************************************************************************/ |
| 59 | #define TEGRA_CONSOLE_BAUDRATE 115200 |
| 60 | #define TEGRA_BOOT_UART_CLK_IN_HZ 408000000 |
| 61 | |
| 62 | /******************************************************************************* |
| 63 | * Platform memory map related constants |
| 64 | ******************************************************************************/ |
| 65 | /* Size of trusted dram */ |
| 66 | #define TZDRAM_SIZE 0x00400000 |
| 67 | #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) |
| 68 | |
| 69 | /******************************************************************************* |
| 70 | * BL31 specific defines. |
| 71 | ******************************************************************************/ |
| Varun Wadekar | 52a1598 | 2015-06-05 12:57:27 +0530 | [diff] [blame] | 72 | #define BL31_SIZE 0x20000 |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 73 | #define BL31_BASE TZDRAM_BASE |
| Varun Wadekar | 52a1598 | 2015-06-05 12:57:27 +0530 | [diff] [blame] | 74 | #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) |
| 75 | #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) |
| 76 | #define BL32_LIMIT TZDRAM_END |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 77 | |
| 78 | /******************************************************************************* |
| 79 | * Platform specific page table and MMU setup constants |
| 80 | ******************************************************************************/ |
| 81 | #define ADDR_SPACE_SIZE (1ull << 32) |
| 82 | #define MAX_XLAT_TABLES 3 |
| 83 | #define MAX_MMAP_REGIONS 8 |
| 84 | |
| 85 | /******************************************************************************* |
| 86 | * Some data must be aligned on the biggest cache line size in the platform. |
| 87 | * This is known only to the platform as it might have a combination of |
| 88 | * integrated and external caches. |
| 89 | ******************************************************************************/ |
| 90 | #define CACHE_WRITEBACK_SHIFT 6 |
| 91 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 92 | |
| 93 | #endif /* __PLATFORM_DEF_H__ */ |