Jit Loon Lim | 55bf238 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef DDR_H |
| 8 | #define DDR_H |
| 9 | |
| 10 | #include <lib/mmio.h> |
| 11 | #include "socfpga_handoff.h" |
| 12 | |
| 13 | /* MACRO DEFINATION */ |
| 14 | #define IO96B_0_REG_BASE 0x18400000 |
| 15 | #define IO96B_1_REG_BASE 0x18800000 |
| 16 | #define IO96B_CSR_BASE 0x05000000 |
| 17 | #define IO96B_CSR_REG(reg) (IO96B_CSR_BASE + reg) |
| 18 | |
| 19 | #define IOSSM_CMD_MAX_WORD_SIZE 7U |
| 20 | #define IOSSM_RESP_MAX_WORD_SIZE 4U |
| 21 | |
| 22 | #define CCU_REG_BASE 0x1C000000 |
| 23 | #define DMI0_DMIUSMCTCR 0x7300 |
| 24 | #define DMI1_DMIUSMCTCR 0x8300 |
| 25 | #define CCU_DMI_ALLOCEN BIT(1) |
| 26 | #define CCU_DMI_LOOKUPEN BIT(2) |
| 27 | #define CCU_REG(reg) (CCU_REG_BASE + reg) |
| 28 | |
| 29 | // CMD_RESPONSE_STATUS Register |
| 30 | #define CMD_RESPONSE_STATUS 0x45C |
| 31 | #define CMD_RESPONSE_OFFSET 0x4 |
| 32 | #define CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16) |
| 33 | #define CMD_RESPONSE_DATA_SHORT_OFFSET 16 |
| 34 | #define STATUS_CMD_RESPONSE_ERROR_MASK GENMASK(7, 5) |
| 35 | #define STATUS_CMD_RESPONSE_ERROR_OFFSET 5 |
| 36 | #define STATUS_GENERAL_ERROR_MASK GENMASK(4, 1) |
| 37 | #define STATUS_GENERAL_ERROR_OFFSET 1 |
| 38 | #define STATUS_COMMAND_RESPONSE_READY 0x1 |
| 39 | #define STATUS_COMMAND_RESPONSE_READY_CLEAR 0x0 |
| 40 | #define STATUS_COMMAND_RESPONSE_READY_MASK 0x1 |
| 41 | #define STATUS_COMMAND_RESPONSE_READY_OFFSET 0 |
| 42 | #define STATUS_COMMAND_RESPONSE(x) (((x) & \ |
| 43 | STATUS_COMMAND_RESPONSE_READY_MASK) >> \ |
| 44 | STATUS_COMMAND_RESPONSE_READY_OFFSET) |
| 45 | |
| 46 | // CMD_REQ Register |
| 47 | #define CMD_STATUS 0x400 |
| 48 | #define CMD_PARAM 0x438 |
| 49 | #define CMD_REQ 0x43C |
| 50 | #define CMD_PARAM_OFFSET 0x4 |
| 51 | #define CMD_TARGET_IP_TYPE_MASK GENMASK(31, 29) |
| 52 | #define CMD_TARGET_IP_TYPE_OFFSET 29 |
| 53 | #define CMD_TARGET_IP_INSTANCE_ID_MASK GENMASK(28, 24) |
| 54 | #define CMD_TARGET_IP_INSTANCE_ID_OFFSET 24 |
| 55 | #define CMD_TYPE_MASK GENMASK(23, 16) |
| 56 | #define CMD_TYPE_OFFSET 16 |
| 57 | #define CMD_OPCODE_MASK GENMASK(15, 0) |
| 58 | #define CMD_OPCODE_OFFSET 0 |
| 59 | |
| 60 | #define CMD_INIT 0 |
| 61 | |
| 62 | #define OPCODE_GET_MEM_INTF_INFO 0x0001 |
| 63 | #define OPCODE_GET_MEM_TECHNOLOGY 0x0002 |
| 64 | #define OPCODE_GET_MEM_WIDTH_INFO 0x0004 |
| 65 | #define OPCODE_TRIG_MEM_CAL 0x000A |
| 66 | #define OPCODE_ECC_ENABLE_STATUS 0x0102 |
| 67 | #define OPCODE_ECC_INTERRUPT_MASK 0x0105 |
| 68 | #define OPCODE_ECC_SCRUB_MODE_0_START 0x0202 |
| 69 | #define OPCODE_ECC_SCRUB_MODE_1_START 0x0203 |
| 70 | #define OPCODE_BIST_RESULTS_STATUS 0x0302 |
| 71 | #define OPCODE_BIST_MEM_INIT_START 0x0303 |
| 72 | // Please update according to IOSSM mailbox spec |
| 73 | #define MBOX_ID_IOSSM 0x00 |
| 74 | #define MBOX_CMD_GET_SYS_INFO 0x01 |
| 75 | // Please update according to IOSSM mailbox spec |
| 76 | #define MBOX_CMD_GET_MEM_INFO 0x02 |
| 77 | #define MBOX_CMD_TRIG_CONTROLLER_OP 0x04 |
| 78 | #define MBOX_CMD_TRIG_MEM_CAL_OP 0x05 |
| 79 | #define MBOX_CMD_POKE_REG 0xFD |
| 80 | #define MBOX_CMD_PEEK_REG 0xFE |
| 81 | #define MBOX_CMD_GET_DEBUG_LOG 0xFF |
| 82 | // Please update according to IOSSM mailbox spec |
| 83 | #define MBOX_CMD_DIRECT 0x00 |
| 84 | |
| 85 | #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_0_MASK 0x01 |
| 86 | |
| 87 | #define IOSSM_MB_WRITE(addr, data) mmio_write_32(addr, data) |
| 88 | |
| 89 | /* FUNCTION DEFINATION */ |
| 90 | int ddr_calibration_check(void); |
| 91 | |
| 92 | int iossm_mb_init(void); |
| 93 | |
| 94 | int iossm_mb_read_response(void); |
| 95 | |
| 96 | int iossm_mb_send(uint32_t cmd_target_ip_type, uint32_t cmd_target_ip_instance_id, |
| 97 | uint32_t cmd_type, uint32_t cmd_opcode, uint32_t *args, |
| 98 | unsigned int len); |
| 99 | |
| 100 | int ddr_iossm_mailbox_cmd(uint32_t cmd); |
| 101 | |
| 102 | int ddr_init(void); |
| 103 | |
| 104 | int ddr_config_handoff(handoff *hoff_ptr); |
| 105 | |
| 106 | void ddr_enable_ns_access(void); |
| 107 | |
| 108 | void ddr_enable_firewall(void); |
| 109 | |
| 110 | bool is_ddr_init_in_progress(void); |
| 111 | |
| 112 | #endif |