| Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 5 | */ |
| 6 | #include <arch.h> |
| 7 | #include <asm_macros.S> |
| 8 | #include <bl_common.h> |
| 9 | #include <cortex_a73.h> |
| 10 | #include <cpu_macros.S> |
| 11 | #include <plat_macros.S> |
| 12 | |
| 13 | /* --------------------------------------------- |
| 14 | * Disable L1 data cache |
| 15 | * --------------------------------------------- |
| 16 | */ |
| 17 | func cortex_a73_disable_dcache |
| 18 | mrs x1, sctlr_el3 |
| 19 | bic x1, x1, #SCTLR_C_BIT |
| 20 | msr sctlr_el3, x1 |
| 21 | isb |
| 22 | ret |
| 23 | endfunc cortex_a73_disable_dcache |
| 24 | |
| 25 | /* --------------------------------------------- |
| 26 | * Disable intra-cluster coherency |
| 27 | * --------------------------------------------- |
| 28 | */ |
| 29 | func cortex_a73_disable_smp |
| 30 | mrs x0, CORTEX_A73_CPUECTLR_EL1 |
| 31 | bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT |
| 32 | msr CORTEX_A73_CPUECTLR_EL1, x0 |
| 33 | isb |
| 34 | dsb sy |
| 35 | ret |
| 36 | endfunc cortex_a73_disable_smp |
| 37 | |
| 38 | func cortex_a73_reset_func |
| 39 | /* --------------------------------------------- |
| 40 | * Enable the SMP bit. |
| 41 | * Clobbers : x0 |
| 42 | * --------------------------------------------- |
| 43 | */ |
| 44 | mrs x0, CORTEX_A73_CPUECTLR_EL1 |
| 45 | orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT |
| 46 | msr CORTEX_A73_CPUECTLR_EL1, x0 |
| 47 | isb |
| 48 | ret |
| 49 | endfunc cortex_a73_reset_func |
| 50 | |
| 51 | func cortex_a73_core_pwr_dwn |
| 52 | mov x18, x30 |
| 53 | |
| 54 | /* --------------------------------------------- |
| 55 | * Turn off caches. |
| 56 | * --------------------------------------------- |
| 57 | */ |
| 58 | bl cortex_a73_disable_dcache |
| 59 | |
| 60 | /* --------------------------------------------- |
| 61 | * Flush L1 caches. |
| 62 | * --------------------------------------------- |
| 63 | */ |
| 64 | mov x0, #DCCISW |
| 65 | bl dcsw_op_level1 |
| 66 | |
| 67 | /* --------------------------------------------- |
| 68 | * Come out of intra cluster coherency |
| 69 | * --------------------------------------------- |
| 70 | */ |
| 71 | mov x30, x18 |
| 72 | b cortex_a73_disable_smp |
| 73 | endfunc cortex_a73_core_pwr_dwn |
| 74 | |
| 75 | func cortex_a73_cluster_pwr_dwn |
| 76 | mov x18, x30 |
| 77 | |
| 78 | /* --------------------------------------------- |
| 79 | * Turn off caches. |
| 80 | * --------------------------------------------- |
| 81 | */ |
| 82 | bl cortex_a73_disable_dcache |
| 83 | |
| 84 | /* --------------------------------------------- |
| 85 | * Flush L1 caches. |
| 86 | * --------------------------------------------- |
| 87 | */ |
| 88 | mov x0, #DCCISW |
| 89 | bl dcsw_op_level1 |
| 90 | |
| 91 | /* --------------------------------------------- |
| 92 | * Disable the optional ACP. |
| 93 | * --------------------------------------------- |
| 94 | */ |
| 95 | bl plat_disable_acp |
| 96 | |
| 97 | /* --------------------------------------------- |
| 98 | * Flush L2 caches. |
| 99 | * --------------------------------------------- |
| 100 | */ |
| 101 | mov x0, #DCCISW |
| 102 | bl dcsw_op_level2 |
| 103 | |
| 104 | /* --------------------------------------------- |
| 105 | * Come out of intra cluster coherency |
| 106 | * --------------------------------------------- |
| 107 | */ |
| 108 | mov x30, x18 |
| 109 | b cortex_a73_disable_smp |
| 110 | endfunc cortex_a73_cluster_pwr_dwn |
| 111 | |
| 112 | /* --------------------------------------------- |
| 113 | * This function provides cortex_a73 specific |
| 114 | * register information for crash reporting. |
| 115 | * It needs to return with x6 pointing to |
| 116 | * a list of register names in ascii and |
| 117 | * x8 - x15 having values of registers to be |
| 118 | * reported. |
| 119 | * --------------------------------------------- |
| 120 | */ |
| 121 | .section .rodata.cortex_a73_regs, "aS" |
| 122 | cortex_a73_regs: /* The ascii list of register names to be reported */ |
| Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 123 | .asciz "cpuectlr_el1", "l2merrsr_el1", "" |
| Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 124 | |
| 125 | func cortex_a73_cpu_reg_dump |
| 126 | adr x6, cortex_a73_regs |
| 127 | mrs x8, CORTEX_A73_CPUECTLR_EL1 |
| Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 128 | mrs x9, CORTEX_A73_L2MERRSR_EL1 |
| Yatharth Kochar | 63af687 | 2016-02-09 12:00:03 +0000 | [diff] [blame] | 129 | ret |
| 130 | endfunc cortex_a73_cpu_reg_dump |
| 131 | |
| Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 132 | declare_cpu_ops cortex_a73, CORTEX_A73_MIDR, \ |
| 133 | cortex_a73_reset_func, \ |
| 134 | cortex_a73_core_pwr_dwn, \ |
| 135 | cortex_a73_cluster_pwr_dwn |