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Varun Wadekarb316e242015-05-19 16:48:04 +05301#
Varun Wadekared3c62b2017-03-06 09:15:15 -08002# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05303#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are met:
6#
7# Redistributions of source code must retain the above copyright notice, this
8# list of conditions and the following disclaimer.
9#
10# Redistributions in binary form must reproduce the above copyright notice,
11# this list of conditions and the following disclaimer in the documentation
12# and/or other materials provided with the distribution.
13#
14# Neither the name of ARM nor the names of its contributors may be used
15# to endorse or promote products derived from this software without specific
16# prior written permission.
17#
18# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28# POSSIBILITY OF SUCH DAMAGE.
29#
30
Varun Wadekar1edb8822016-09-01 14:59:32 -070031TZDRAM_BASE := 0xFF800000
Varun Wadekarb316e242015-05-19 16:48:04 +053032$(eval $(call add_define,TZDRAM_BASE))
33
34ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT := 1
35$(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT))
36
Varun Wadekard1b61502015-07-16 09:46:28 +053037PLATFORM_CLUSTER_COUNT := 2
Varun Wadekarb316e242015-05-19 16:48:04 +053038$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
39
Varun Wadekard1b61502015-07-16 09:46:28 +053040PLATFORM_MAX_CPUS_PER_CLUSTER := 4
Varun Wadekarb316e242015-05-19 16:48:04 +053041$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
42
Steven Kao4d160ac2016-12-23 16:05:13 +080043MAX_XLAT_TABLES := 4
Varun Wadekar97f24902015-09-09 11:29:24 +053044$(eval $(call add_define,MAX_XLAT_TABLES))
45
46MAX_MMAP_REGIONS := 8
47$(eval $(call add_define,MAX_MMAP_REGIONS))
48
Varun Wadekar5f4e6432015-07-21 11:53:35 +053049BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
50 lib/cpus/aarch64/cortex_a57.S \
Varun Wadekara1176ba2015-08-25 17:01:06 +053051 ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
Varun Wadekar7a9a2852015-09-18 11:21:22 +053052 ${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \
Varun Wadekar5f4e6432015-07-21 11:53:35 +053053 ${SOC_DIR}/plat_psci_handlers.c \
54 ${SOC_DIR}/plat_setup.c \
Varun Wadekarb316e242015-05-19 16:48:04 +053055 ${SOC_DIR}/plat_secondary.c
56
Varun Wadekared3c62b2017-03-06 09:15:15 -080057# Enable workarounds for selected Cortex-A57 erratas.
58A57_DISABLE_NON_TEMPORAL_HINT := 1
59ERRATA_A57_826974 := 1
60ERRATA_A57_826977 := 1
61ERRATA_A57_828024 := 1
62ERRATA_A57_829520 := 1
63ERRATA_A57_833471 := 1
Varun Wadekard1b61502015-07-16 09:46:28 +053064
Varun Wadekared3c62b2017-03-06 09:15:15 -080065# Enable workarounds for selected Cortex-A53 erratas.
66A53_DISABLE_NON_TEMPORAL_HINT := 1
67ERRATA_A53_826319 := 1
68ERRATA_A53_836870 := 1
Andre Przywara1108fc62016-11-07 10:53:14 +000069ERRATA_A53_855873 := 1