| Yatharth Kochar | 5d36121 | 2016-06-28 17:07:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <asm_macros.S> |
| 33 | #include <bl1.h> |
| 34 | #include <bl_common.h> |
| 35 | |
| 36 | .globl bl1_aarch32_smc_handler |
| 37 | |
| 38 | |
| 39 | func bl1_aarch32_smc_handler |
| 40 | /* ------------------------------------------------ |
| 41 | * SMC in BL1 is handled assuming that the MMU is |
| 42 | * turned off by BL2. |
| 43 | * ------------------------------------------------ |
| 44 | */ |
| 45 | |
| 46 | /* ---------------------------------------------- |
| 47 | * Only RUN_IMAGE SMC is supported. |
| 48 | * ---------------------------------------------- |
| 49 | */ |
| 50 | mov r8, #BL1_SMC_RUN_IMAGE |
| 51 | cmp r8, r0 |
| 52 | blne report_exception |
| 53 | |
| 54 | /* ------------------------------------------------ |
| 55 | * Make sure only Secure world reaches here. |
| 56 | * ------------------------------------------------ |
| 57 | */ |
| 58 | ldcopr r8, SCR |
| 59 | tst r8, #SCR_NS_BIT |
| 60 | blne report_exception |
| 61 | |
| 62 | /* --------------------------------------------------------------------- |
| 63 | * Pass control to next secure image. |
| 64 | * Here it expects r1 to contain the address of a entry_point_info_t |
| 65 | * structure describing the BL entrypoint. |
| 66 | * --------------------------------------------------------------------- |
| 67 | */ |
| 68 | mov r8, r1 |
| 69 | mov r0, r1 |
| 70 | bl bl1_print_next_bl_ep_info |
| 71 | |
| 72 | #if SPIN_ON_BL1_EXIT |
| 73 | bl print_debug_loop_message |
| 74 | debug_loop: |
| 75 | b debug_loop |
| 76 | #endif |
| 77 | |
| 78 | mov r0, r8 |
| 79 | bl bl1_plat_prepare_exit |
| 80 | |
| 81 | stcopr r0, TLBIALL |
| 82 | dsb sy |
| 83 | isb |
| 84 | |
| 85 | /* |
| 86 | * Extract PC and SPSR based on struct `entry_point_info_t` |
| 87 | * and load it in LR and SPSR registers respectively. |
| 88 | */ |
| 89 | ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET] |
| 90 | ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] |
| 91 | msr spsr, r1 |
| 92 | |
| 93 | add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET |
| 94 | ldm r8, {r0, r1, r2, r3} |
| 95 | eret |
| 96 | endfunc bl1_aarch32_smc_handler |