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Soby Mathew47e43f22016-02-01 14:04:34 +00001/*
Aditya Angadi7f8837b2019-12-31 14:23:53 +05302 * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
Soby Mathew47e43f22016-02-01 14:04:34 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew47e43f22016-02-01 14:04:34 +00005 */
6
Antonio Nino Diaz1b0c6f12019-01-23 21:08:43 +00007#include <drivers/arm/css/css_mhu_doorbell.h>
Antonio Nino Diazc30db5b2019-01-23 20:37:32 +00008#include <drivers/arm/css/scmi.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +00009#include <plat/arm/common/plat_arm.h>
10#include <plat/arm/css/common/css_pm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <plat/common/platform.h>
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +000012#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013
Sudeep Holla52c7ab32018-11-01 16:17:30 +000014#if CSS_USE_SCMI_SDS_DRIVER
Chandni Cherukuri61f3a7c2018-10-11 14:08:08 +053015static scmi_channel_plat_info_t juno_scmi_plat_info = {
16 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
17 .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
18 .db_preserve_mask = 0xfffffffe,
19 .db_modify_mask = 0x1,
20 .ring_doorbell = &mhu_ring_doorbell,
21};
22
Aditya Angadi7f8837b2019-12-31 14:23:53 +053023scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
Chandni Cherukuri61f3a7c2018-10-11 14:08:08 +053024{
25 return &juno_scmi_plat_info;
26}
Soby Mathew47e43f22016-02-01 14:04:34 +000027
Sudeep Holla52c7ab32018-11-01 16:17:30 +000028#endif
Soby Mathew47e43f22016-02-01 14:04:34 +000029/*
30 * On Juno, the system power level is the highest power level.
31 * The first entry in the power domain descriptor specifies the
32 * number of system power domains i.e. 1.
33 */
34#define JUNO_PWR_DOMAINS_AT_MAX_PWR_LVL ARM_SYSTEM_COUNT
35
36/*
37 * The Juno power domain tree descriptor. The cluster power domains
38 * are arranged so that when the PSCI generic code creates the power
39 * domain tree, the indices of the CPU power domain nodes it allocates
40 * match the linear indices returned by plat_core_pos_by_mpidr()
41 * i.e. CLUSTER1 CPUs are allocated indices from 0 to 3 and the higher
42 * indices for CLUSTER0 CPUs.
43 */
Roberto Vargas2b36b152018-02-12 12:36:17 +000044static const unsigned char juno_power_domain_tree_desc[] = {
Soby Mathew47e43f22016-02-01 14:04:34 +000045 /* No of root nodes */
46 JUNO_PWR_DOMAINS_AT_MAX_PWR_LVL,
47 /* No of children for the root node */
48 JUNO_CLUSTER_COUNT,
49 /* No of children for the first cluster node */
50 JUNO_CLUSTER1_CORE_COUNT,
51 /* No of children for the second cluster node */
52 JUNO_CLUSTER0_CORE_COUNT
53};
54
55/*******************************************************************************
56 * This function returns the Juno topology tree information.
57 ******************************************************************************/
58const unsigned char *plat_get_power_domain_tree_desc(void)
59{
60 return juno_power_domain_tree_desc;
61}
62
63/*******************************************************************************
64 * This function returns the core count within the cluster corresponding to
65 * `mpidr`.
66 ******************************************************************************/
67unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
68{
Sathees Balya30952cc2018-09-27 14:41:02 +010069 return (((mpidr & (u_register_t) 0x100) != 0U) ?
70 JUNO_CLUSTER1_CORE_COUNT : JUNO_CLUSTER0_CORE_COUNT);
Soby Mathew47e43f22016-02-01 14:04:34 +000071}
Soby Mathewcbafd7a2016-11-14 12:44:32 +000072
73/*
74 * The array mapping platform core position (implemented by plat_my_core_pos())
75 * to the SCMI power domain ID implemented by SCP.
76 */
77const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[PLATFORM_CORE_COUNT] = {
78 2, 3, 4, 5, 0, 1 };