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Rex-BC Chenabd9ecf2021-10-06 19:25:50 +08001/*
jason-ch chena07e3ea2021-11-16 10:18:46 +08002 * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
Rex-BC Chenabd9ecf2021-10-06 19:25:50 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/debug.h>
8#include <common/runtime_svc.h>
jason-ch chena07e3ea2021-11-16 10:18:46 +08009#include <mt_spm_vcorefs.h>
10#include <mtk_sip_svc.h>
11#include "plat_sip_calls.h"
Rex-BC Chenabd9ecf2021-10-06 19:25:50 +080012
13uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
14 u_register_t x1,
15 u_register_t x2,
16 u_register_t x3,
17 u_register_t x4,
18 void *cookie,
19 void *handle,
20 u_register_t flags)
21{
jason-ch chena07e3ea2021-11-16 10:18:46 +080022 uint64_t ret;
23
Rex-BC Chenabd9ecf2021-10-06 19:25:50 +080024 switch (smc_fid) {
jason-ch chena07e3ea2021-11-16 10:18:46 +080025 case MTK_SIP_VCORE_CONTROL_ARCH32:
26 case MTK_SIP_VCORE_CONTROL_ARCH64:
27 ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4);
28 SMC_RET2(handle, ret, x4);
29 break;
Rex-BC Chenabd9ecf2021-10-06 19:25:50 +080030 default:
31 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
32 break;
33 }
34
35 SMC_RET1(handle, SMC_UNK);
36}