Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / bbd0f5a9bd0b7dc45393c2089d4ff7756d3075cb / . / drivers / staging / renesas / rcar / qos / H3 / qos_init_h3_v10.c
blob: 21aa3df039f02b19ecea56f9dc09260e85b67372 [file] [log] [blame]
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1/*
2 * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]8
9#include <common/debug.h>
10
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]11#include "../qos_common.h"
12#include "qos_init_h3_v10.h"
13
14#define RCAR_QOS_VERSION "rev.0.36"
15
16#define RCAR_QOS_NONE (3U)
17#define RCAR_QOS_TYPE_DEFAULT (0U)
18
19#define RCAR_DRAM_SPLIT_LINEAR (0U)
20#define RCAR_DRAM_SPLIT_4CH (1U)
21#define RCAR_DRAM_SPLIT_2CH (2U)
22#define RCAR_DRAM_SPLIT_AUTO (3U)
23
24#define AXI_BASE (0xE6784000U)
25#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
26#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
27#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
28#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
29#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
30#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
31#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
32#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
33#define ADSPLCR0_SWP (0x0CU)
34
35#define MSTAT_BASE (0xE67E0000U)
36#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
37#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
38#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
39#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
40#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
41#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
42#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
43
44#define RALLOC_BASE (0xE67F0000U)
45#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
46#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
47#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
48#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
49#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
50#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
51#define RALLOC_EC (RALLOC_BASE + 0x003CU)
52#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
53#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
54#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
55
56#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
57static const mstat_slot_t mstat_fix[] = {
58 {0x0000U, 0x0000000000000000UL},
59 {0x0008U, 0x0000000000000000UL},
60 {0x0010U, 0x0000000000000000UL},
61 {0x0018U, 0x0000000000000000UL},
62 {0x0020U, 0x0000000000000000UL},
63 {0x0028U, 0x0000000000000000UL},
64 {0x0030U, 0x0000000000000000UL},
65 {0x0038U, 0x0000000000000000UL},
66 {0x0040U, 0x00140C050000FFFFUL},
67 {0x0048U, 0x0000000000000000UL},
68 {0x0050U, 0x0000000000000000UL},
69 {0x0058U, 0x001404030000FFFFUL},
70 {0x0060U, 0x001408060000FFFFUL},
71 {0x0068U, 0x0000000000000000UL},
72 {0x0070U, 0x0000000000000000UL},
73 {0x0078U, 0x0000000000000000UL},
74 {0x0080U, 0x0000000000000000UL},
75 {0x0088U, 0x00140C050000FFFFUL},
76 {0x0090U, 0x001408060000FFFFUL},
77 {0x0098U, 0x001404020000FFFFUL},
78 {0x00A0U, 0x0000000000000000UL},
79 {0x00A8U, 0x0000000000000000UL},
80 {0x00B0U, 0x0000000000000000UL},
81 {0x00B8U, 0x0000000000000000UL},
82 {0x00C0U, 0x0000000000000000UL},
83 {0x00C8U, 0x0000000000000000UL},
84 {0x00D0U, 0x0000000000000000UL},
85 {0x00D8U, 0x0000000000000000UL},
86 {0x00E0U, 0x0000000000000000UL},
87 {0x00E8U, 0x0000000000000000UL},
88 {0x00F0U, 0x0000000000000000UL},
89 {0x00F8U, 0x0000000000000000UL},
90 {0x0100U, 0x0000000000000000UL},
91 {0x0108U, 0x0000000000000000UL},
92 {0x0110U, 0x0000000000000000UL},
93 {0x0118U, 0x0000000000000000UL},
94 {0x0120U, 0x0000000000000000UL},
95 {0x0128U, 0x0000000000000000UL},
96 {0x0130U, 0x0000000000000000UL},
97 {0x0138U, 0x001004020000FFFFUL},
98 {0x0140U, 0x001004020000FFFFUL},
99 {0x0148U, 0x001004020000FFFFUL},
100 {0x0150U, 0x001008050000FFFFUL},
101 {0x0158U, 0x001008050000FFFFUL},
102 {0x0160U, 0x001008050000FFFFUL},
103 {0x0168U, 0x001008050000FFFFUL},
104 {0x0170U, 0x001008050000FFFFUL},
105 {0x0178U, 0x001004030000FFFFUL},
106 {0x0180U, 0x001004030000FFFFUL},
107 {0x0188U, 0x001004030000FFFFUL},
108 {0x0190U, 0x001014140000FFFFUL},
109 {0x0198U, 0x001014140000FFFFUL},
110 {0x01A0U, 0x001008060000FFFFUL},
111 {0x01A8U, 0x001008060000FFFFUL},
112 {0x01B0U, 0x001008060000FFFFUL},
113 {0x01B8U, 0x0000000000000000UL},
114 {0x01C0U, 0x0000000000000000UL},
115 {0x01C8U, 0x0000000000000000UL},
116 {0x01D0U, 0x0000000000000000UL},
117 {0x01D8U, 0x0000000000000000UL},
118 {0x01E0U, 0x0000000000000000UL},
119 {0x01E8U, 0x0000000000000000UL},
120 {0x01F0U, 0x0000000000000000UL},
121 {0x01F8U, 0x0000000000000000UL},
122 {0x0200U, 0x0000000000000000UL},
123 {0x0208U, 0x0000000000000000UL},
124 {0x0210U, 0x0000000000000000UL},
125 {0x0218U, 0x0000000000000000UL},
126 {0x0220U, 0x0000000000000000UL},
127 {0x0228U, 0x0000000000000000UL},
128 {0x0230U, 0x0000000000000000UL},
129 {0x0238U, 0x0000000000000000UL},
130 {0x0240U, 0x0000000000000000UL},
131 {0x0248U, 0x0000000000000000UL},
132 {0x0250U, 0x0000000000000000UL},
133 {0x0258U, 0x0000000000000000UL},
134 {0x0260U, 0x0000000000000000UL},
135 {0x0268U, 0x0000000000000000UL},
136 {0x0270U, 0x0000000000000000UL},
137 {0x0278U, 0x0000000000000000UL},
138 {0x0280U, 0x0000000000000000UL},
139 {0x0288U, 0x0000000000000000UL},
140 {0x0290U, 0x0000000000000000UL},
141 {0x0298U, 0x0000000000000000UL},
142 {0x02A0U, 0x0000000000000000UL},
143 {0x02A8U, 0x0000000000000000UL},
144 {0x02B0U, 0x0000000000000000UL},
145 {0x02B8U, 0x0000000000000000UL},
146 {0x02C0U, 0x0000000000000000UL},
147 {0x02C8U, 0x0000000000000000UL},
148 {0x02D0U, 0x0000000000000000UL},
149 {0x02D8U, 0x0000000000000000UL},
150 {0x02E0U, 0x0000000000000000UL},
151 {0x02E8U, 0x0000000000000000UL},
152 {0x02F0U, 0x0000000000000000UL},
153 {0x02F8U, 0x0000000000000000UL},
154 {0x0300U, 0x0000000000000000UL},
155 {0x0308U, 0x0000000000000000UL},
156 {0x0310U, 0x0000000000000000UL},
157 {0x0318U, 0x0000000000000000UL},
158 {0x0320U, 0x0000000000000000UL},
159 {0x0328U, 0x0000000000000000UL},
160 {0x0330U, 0x0000000000000000UL},
161 {0x0338U, 0x0000000000000000UL},
162};
163
164static const mstat_slot_t mstat_be[] = {
165 {0x0000U, 0x001000100C8FFC01UL},
166 {0x0008U, 0x001000100C8FFC01UL},
167 {0x0010U, 0x001000100C8FFC01UL},
168 {0x0018U, 0x001000100C8FFC01UL},
169 {0x0020U, 0x001000100C8FFC01UL},
170 {0x0028U, 0x001000100C8FFC01UL},
171 {0x0030U, 0x001000100C8FFC01UL},
172 {0x0038U, 0x001000100C8FFC01UL},
173 {0x0040U, 0x0000000000000000UL},
174 {0x0048U, 0x0000000000000000UL},
175 {0x0050U, 0x001000100C8FFC01UL},
176 {0x0058U, 0x0000000000000000UL},
177 {0x0060U, 0x0000000000000000UL},
178 {0x0068U, 0x001000100C8FFC01UL},
179 {0x0070U, 0x001000100C8FFC01UL},
180 {0x0078U, 0x001000100C8FFC01UL},
181 {0x0080U, 0x001000100C8FFC01UL},
182 {0x0088U, 0x0000000000000000UL},
183 {0x0090U, 0x0000000000000000UL},
184 {0x0098U, 0x0000000000000000UL},
185 {0x00A0U, 0x001000100C8FFC01UL},
186 {0x00A8U, 0x001000100C8FFC01UL},
187 {0x00B0U, 0x001000100C8FFC01UL},
188 {0x00B8U, 0x001000100C8FFC01UL},
189 {0x00C0U, 0x001000100C8FFC01UL},
190 {0x00C8U, 0x001000100C8FFC01UL},
191 {0x00D0U, 0x001000100C8FFC01UL},
192 {0x00D8U, 0x002000200C8FFC01UL},
193 {0x00E0U, 0x002000200C8FFC01UL},
194 {0x00E8U, 0x001000100C8FFC01UL},
195 {0x00F0U, 0x001000100C8FFC01UL},
196 {0x00F8U, 0x001000100C8FFC01UL},
197 {0x0100U, 0x0000000000000000UL},
198 {0x0108U, 0x002000200C8FFC01UL},
199 {0x0110U, 0x001000100C8FFC01UL},
200 {0x0118U, 0x001000100C8FFC01UL},
201 {0x0120U, 0x0000000000000000UL},
202 {0x0128U, 0x002000200C8FFC01UL},
203 {0x0130U, 0x001000100C8FFC01UL},
204 {0x0138U, 0x0000000000000000UL},
205 {0x0140U, 0x0000000000000000UL},
206 {0x0148U, 0x0000000000000000UL},
207 {0x0150U, 0x0000000000000000UL},
208 {0x0158U, 0x0000000000000000UL},
209 {0x0160U, 0x0000000000000000UL},
210 {0x0168U, 0x0000000000000000UL},
211 {0x0170U, 0x0000000000000000UL},
212 {0x0178U, 0x0000000000000000UL},
213 {0x0180U, 0x0000000000000000UL},
214 {0x0188U, 0x0000000000000000UL},
215 {0x0190U, 0x0000000000000000UL},
216 {0x0198U, 0x0000000000000000UL},
217 {0x01A0U, 0x0000000000000000UL},
218 {0x01A8U, 0x0000000000000000UL},
219 {0x01B0U, 0x0000000000000000UL},
220 {0x01B8U, 0x001000100C8FFC01UL},
221 {0x01C0U, 0x001000200C8FFC01UL},
222 {0x01C8U, 0x001000200C8FFC01UL},
223 {0x01D0U, 0x001000200C8FFC01UL},
224 {0x01D8U, 0x001000200C8FFC01UL},
225 {0x01E0U, 0x001000100C8FFC01UL},
226 {0x01E8U, 0x001000100C8FFC01UL},
227 {0x01F0U, 0x001000100C8FFC01UL},
228 {0x01F8U, 0x001000100C8FFC01UL},
229 {0x0200U, 0x001000100C8FFC01UL},
230 {0x0208U, 0x001000100C8FFC01UL},
231 {0x0210U, 0x001000100C8FFC01UL},
232 {0x0218U, 0x001000100C8FFC01UL},
233 {0x0220U, 0x001000100C8FFC01UL},
234 {0x0228U, 0x001000100C8FFC01UL},
235 {0x0230U, 0x001000100C8FFC01UL},
236 {0x0238U, 0x001000100C8FFC01UL},
237 {0x0240U, 0x001000100C8FFC01UL},
238 {0x0248U, 0x001000100C8FFC01UL},
239 {0x0250U, 0x001000100C8FFC01UL},
240 {0x0258U, 0x001000100C8FFC01UL},
241 {0x0260U, 0x001000100C8FFC01UL},
242 {0x0268U, 0x001000100C8FFC01UL},
243 {0x0270U, 0x001000100C8FFC01UL},
244 {0x0278U, 0x001000100C8FFC01UL},
245 {0x0280U, 0x001000100C8FFC01UL},
246 {0x0288U, 0x001000100C8FFC01UL},
247 {0x0290U, 0x001000100C8FFC01UL},
248 {0x0298U, 0x001000100C8FFC01UL},
249 {0x02A0U, 0x001000100C8FFC01UL},
250 {0x02A8U, 0x001000100C8FFC01UL},
251 {0x02B0U, 0x001000100C8FFC01UL},
252 {0x02B8U, 0x001000100C8FFC01UL},
253 {0x02C0U, 0x001000100C8FFC01UL},
254 {0x02C8U, 0x001000100C8FFC01UL},
255 {0x02D0U, 0x001000100C8FFC01UL},
256 {0x02D8U, 0x001000100C8FFC01UL},
257 {0x02E0U, 0x001000100C8FFC01UL},
258 {0x02E8U, 0x001000100C8FFC01UL},
259 {0x02F0U, 0x001000200C8FFC01UL},
260 {0x02F8U, 0x001000300C8FFC01UL},
261 {0x0300U, 0x0000000000000000UL},
262 {0x0308U, 0x001000200C8FFC01UL},
263 {0x0310U, 0x001000300C8FFC01UL},
264 {0x0318U, 0x0000000000000000UL},
265 {0x0320U, 0x001000200C8FFC01UL},
266 {0x0328U, 0x001000300C8FFC01UL},
267 {0x0330U, 0x001000200C8FFC01UL},
268 {0x0338U, 0x001000300C8FFC01UL},
269};
270#endif
271
272void qos_init_h3_v10(void)
273{
274 /* DRAM Split Address mapping */
275#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
276 (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
277 NOTICE("BL2: DRAM Split is 4ch\n");
278 io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
279 | ADSPLCR0_SPLITSEL(0xFFU)
280 | ADSPLCR0_AREA(0x1BU)
281 | ADSPLCR0_SWP);
282 io_write_32(AXI_ADSPLCR1, 0x00000000U);
283 io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
284 io_write_32(AXI_ADSPLCR3, 0x00000000U);
285#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
286 NOTICE("BL2: DRAM Split is 2ch\n");
287 io_write_32(AXI_ADSPLCR0, 0x00000000U);
288 io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
289 | ADSPLCR0_SPLITSEL(0xFFU)
290 | ADSPLCR0_AREA(0x1BU)
291 | ADSPLCR0_SWP);
292 io_write_32(AXI_ADSPLCR2, 0x00000000U);
293 io_write_32(AXI_ADSPLCR3, 0x00000000U);
294#else
295 NOTICE("BL2: DRAM Split is OFF\n");
296#endif
297
298#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
299#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
300 NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
301#endif
302
303 /* AR Cache setting */
304 io_write_32(0xE67D1000U, 0x00000100U);
305 io_write_32(0xE67D1008U, 0x00000100U);
306
307 /* Resource Alloc setting */
308 io_write_32(RALLOC_RAS, 0x00000040U);
309 io_write_32(RALLOC_FIXTH, 0x000F0005U);
310 io_write_32(RALLOC_REGGD, 0x00000004U);
311 io_write_64(RALLOC_DANN, 0x0202000004040404UL);
312 io_write_32(RALLOC_DANT, 0x003C1110U);
313 io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
314 io_write_64(RALLOC_EMS, 0x0000000000000000UL);
315 io_write_32(RALLOC_INSFC, 0xC7840001U);
316 io_write_32(RALLOC_BERR, 0x00000000U);
317
318 /* MSTAT setting */
319 io_write_32(MSTAT_SL_INIT,
320 SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
321 io_write_32(MSTAT_REF_ARS, 0x00330000U);
322
323 /* MSTAT SRAM setting */
324 for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
325 io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
326 mstat_fix[i].value);
327 io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
328 mstat_fix[i].value);
329 }
330 for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
331 io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
332 mstat_be[i].value);
333 io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
334 mstat_be[i].value);
335 }
336
337 /* 3DG bus Leaf setting */
338 io_write_32(0xFD820808U, 0x00001234U);
339 io_write_32(0xFD820800U, 0x0000003FU);
340 io_write_32(0xFD821800U, 0x0000003FU);
341 io_write_32(0xFD822800U, 0x0000003FU);
342 io_write_32(0xFD823800U, 0x0000003FU);
343 io_write_32(0xFD824800U, 0x0000003FU);
344 io_write_32(0xFD825800U, 0x0000003FU);
345 io_write_32(0xFD826800U, 0x0000003FU);
346 io_write_32(0xFD827800U, 0x0000003FU);
347
348 /* Resource Alloc start */
349 io_write_32(RALLOC_RAEN, 0x00000001U);
350
351 /* MSTAT start */
352 io_write_32(MSTAT_STATQC, 0x00000001U);
353#else
354 NOTICE("BL2: QoS is None\n");
355
356 /* Resource Alloc setting */
357 io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
358#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
359}