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Tony Xief6118cc2016-01-15 17:17:32 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Tony Xief6118cc2016-01-15 17:17:32 +08005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
Tony Xief6118cc2016-01-15 17:17:32 +08009#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/debug.h>
11#include <lib/mmio.h>
12
Tony Xief6118cc2016-01-15 17:17:32 +080013#include <plat_private.h>
14#include <rk3368_def.h>
15#include <soc.h>
16
17static uint32_t plls_con[END_PLL_ID][4];
18
19/* Table of regions to map using the MMU. */
20const mmap_region_t plat_rk_mmap[] = {
21 MAP_REGION_FLAT(CCI400_BASE, CCI400_SIZE,
22 MT_DEVICE | MT_RW | MT_SECURE),
23 MAP_REGION_FLAT(GIC400_BASE, GIC400_SIZE,
24 MT_DEVICE | MT_RW | MT_SECURE),
25 MAP_REGION_FLAT(STIME_BASE, STIME_SIZE,
26 MT_DEVICE | MT_RW | MT_SECURE),
27 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE,
28 MT_DEVICE | MT_RW | MT_SECURE),
29 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE,
30 MT_MEMORY | MT_RW | MT_SECURE),
31 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
32 MT_DEVICE | MT_RW | MT_SECURE),
Christoph Müllner9fecc192019-05-01 01:37:58 +020033 MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
34 MT_DEVICE | MT_RW | MT_SECURE),
35 MAP_REGION_FLAT(UART1_BASE, UART1_SIZE,
36 MT_DEVICE | MT_RW | MT_SECURE),
37 MAP_REGION_FLAT(UART2_BASE, UART2_SIZE,
38 MT_DEVICE | MT_RW | MT_SECURE),
39 MAP_REGION_FLAT(UART3_BASE, UART3_SIZE,
40 MT_DEVICE | MT_RW | MT_SECURE),
41 MAP_REGION_FLAT(UART4_BASE, UART4_SIZE,
Tony Xief6118cc2016-01-15 17:17:32 +080042 MT_DEVICE | MT_RW | MT_SECURE),
43 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
44 MT_DEVICE | MT_RW | MT_SECURE),
45 MAP_REGION_FLAT(DDR_PCTL_BASE, DDR_PCTL_SIZE,
46 MT_DEVICE | MT_RW | MT_SECURE),
47 MAP_REGION_FLAT(DDR_PHY_BASE, DDR_PHY_SIZE,
48 MT_DEVICE | MT_RW | MT_SECURE),
49 MAP_REGION_FLAT(GRF_BASE, GRF_SIZE,
50 MT_DEVICE | MT_RW | MT_SECURE),
51 MAP_REGION_FLAT(SERVICE_BUS_BASE, SERVICE_BUS_SISE,
52 MT_DEVICE | MT_RW | MT_SECURE),
53 { 0 }
54};
55
56/* The RockChip power domain tree descriptor */
57const unsigned char rockchip_power_domain_tree_desc[] = {
58 /* No of root nodes */
59 PLATFORM_SYSTEM_COUNT,
60 /* No of children for the root node */
61 PLATFORM_CLUSTER_COUNT,
62 /* No of children for the first cluster node */
63 PLATFORM_CLUSTER0_CORE_COUNT,
64 /* No of children for the second cluster node */
65 PLATFORM_CLUSTER1_CORE_COUNT
66};
67
68void secure_timer_init(void)
69{
70 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT0, 0xffffffff);
71 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT1, 0xffffffff);
72
73 /* auto reload & enable the timer */
74 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN);
75}
76
77void sgrf_init(void)
78{
79 /* setting all configurable ip into no-secure */
80 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SOC_CON_NS);
81 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SOC_CON7_BITS);
82 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SOC_CON_NS);
83
84 /* secure dma to no sesure */
85 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(0), SGRF_BUSDMAC_CON0_NS);
86 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(1), SGRF_BUSDMAC_CON1_NS);
87 dsb();
88
89 /* rst dma1 */
90 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1),
91 RST_DMA1_MSK | (RST_DMA1_MSK << 16));
92 /* rst dma2 */
93 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4),
94 RST_DMA2_MSK | (RST_DMA2_MSK << 16));
95
96 dsb();
97
98 /* release dma1 rst*/
99 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16));
100 /* release dma2 rst*/
101 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16));
102}
103
104void plat_rockchip_soc_init(void)
105{
106 secure_timer_init();
107 sgrf_init();
108}
109
110void regs_updata_bits(uintptr_t addr, uint32_t val,
111 uint32_t mask, uint32_t shift)
112{
113 uint32_t tmp, orig;
114
115 orig = mmio_read_32(addr);
116
117 tmp = orig & ~(mask << shift);
118 tmp |= (val & mask) << shift;
119
120 if (tmp != orig)
121 mmio_write_32(addr, tmp);
122 dsb();
123}
124
125static void plls_suspend(uint32_t pll_id)
126{
127 plls_con[pll_id][0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0));
128 plls_con[pll_id][1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1));
129 plls_con[pll_id][2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2));
130 plls_con[pll_id][3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3));
131
132 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_SLOW_BITS);
133 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_BYPASS);
134}
135
136static void pm_plls_suspend(void)
137{
138 plls_suspend(NPLL_ID);
139 plls_suspend(CPLL_ID);
140 plls_suspend(GPLL_ID);
141 plls_suspend(ABPLL_ID);
142 plls_suspend(ALPLL_ID);
143}
144
145static inline void plls_resume(void)
146{
147 mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3),
148 plls_con[ABPLL_ID][3] | PLL_BYPASS_W_MSK);
149 mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3),
150 plls_con[ALPLL_ID][3] | PLL_BYPASS_W_MSK);
151 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3),
152 plls_con[GPLL_ID][3] | PLL_BYPASS_W_MSK);
153 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3),
154 plls_con[CPLL_ID][3] | PLL_BYPASS_W_MSK);
155 mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3),
156 plls_con[NPLL_ID][3] | PLL_BYPASS_W_MSK);
157}
158
159void soc_sleep_config(void)
160{
161 int i = 0;
162
163 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++)
164 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000);
165 pm_plls_suspend();
166
167 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++)
168 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000);
169}
170
171void pm_plls_resume(void)
172{
173 plls_resume();
174
175 mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3),
176 plls_con[ABPLL_ID][3] | PLLS_MODE_WMASK);
177 mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3),
178 plls_con[ALPLL_ID][3] | PLLS_MODE_WMASK);
179 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3),
180 plls_con[GPLL_ID][3] | PLLS_MODE_WMASK);
181 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3),
182 plls_con[CPLL_ID][3] | PLLS_MODE_WMASK);
183 mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3),
184 plls_con[NPLL_ID][3] | PLLS_MODE_WMASK);
185}
186
tony.xie3ecb0212017-03-03 16:22:12 +0800187void __dead2 rockchip_soc_soft_reset(void)
Tony Xief6118cc2016-01-15 17:17:32 +0800188{
189 uint32_t temp_val;
190
191 mmio_write_32(CRU_BASE + PLL_CONS((GPLL_ID), 3), PLL_SLOW_BITS);
192 mmio_write_32(CRU_BASE + PLL_CONS((CPLL_ID), 3), PLL_SLOW_BITS);
193 mmio_write_32(CRU_BASE + PLL_CONS((NPLL_ID), 3), PLL_SLOW_BITS);
194 mmio_write_32(CRU_BASE + PLL_CONS((ABPLL_ID), 3), PLL_SLOW_BITS);
195 mmio_write_32(CRU_BASE + PLL_CONS((ALPLL_ID), 3), PLL_SLOW_BITS);
196
197 temp_val = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON) |
198 PMU_RST_BY_SECOND_SFT;
199
200 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, temp_val);
201 mmio_write_32(CRU_BASE + CRU_GLB_SRST_SND, 0xeca8);
202
203 /*
204 * Maybe the HW needs some times to reset the system,
205 * so we do not hope the core to excute valid codes.
206 */
207 while (1)
208 ;
209}