| David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 1 | /* |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. |
| David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef CORTEX_A55_H |
| 8 | #define CORTEX_A55_H |
| David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 9 | |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
| 11 | |
| David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 12 | /* Cortex-A55 MIDR for revision 0 */ |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 13 | #define CORTEX_A55_MIDR U(0x410fd050) |
| David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 14 | |
| 15 | /******************************************************************************* |
| 16 | * CPU Extended Control register specific definitions. |
| 17 | ******************************************************************************/ |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 18 | #define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 19 | #define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 20 | |
| Ambroise Vincent | 6f31960 | 2019-02-21 16:25:37 +0000 | [diff] [blame] | 21 | #define CORTEX_A55_CPUECTLR_EL1_L1WSCTL (ULL(3) << 25) |
| 22 | |
| Ambroise Vincent | 7927fa0 | 2019-02-21 16:20:43 +0000 | [diff] [blame] | 23 | /******************************************************************************* |
| 24 | * CPU Auxiliary Control register specific definitions. |
| 25 | ******************************************************************************/ |
| 26 | #define CORTEX_A55_CPUACTLR_EL1 S3_0_C15_C1_0 |
| 27 | |
| Ambroise Vincent | 6f31960 | 2019-02-21 16:25:37 +0000 | [diff] [blame] | 28 | #define CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING (ULL(1) << 24) |
| Ambroise Vincent | 7927fa0 | 2019-02-21 16:20:43 +0000 | [diff] [blame] | 29 | #define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31) |
| Ambroise Vincent | 6a77f05 | 2019-02-21 16:27:34 +0000 | [diff] [blame] | 30 | #define CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS (ULL(1) << 49) |
| Ambroise Vincent | 7927fa0 | 2019-02-21 16:20:43 +0000 | [diff] [blame] | 31 | |
| Ambroise Vincent | 6f31960 | 2019-02-21 16:25:37 +0000 | [diff] [blame] | 32 | /******************************************************************************* |
| 33 | * CPU Identification register specific definitions. |
| 34 | ******************************************************************************/ |
| 35 | #define CORTEX_A55_CLIDR_EL1 S3_1_C0_C0_1 |
| 36 | |
| 37 | #define CORTEX_A55_CLIDR_EL1_CTYPE3 (ULL(7) << 6) |
| 38 | |
| David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 39 | /* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */ |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 40 | #define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1) |
| David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 41 | |
| Ambroise Vincent | b72fe7a | 2019-05-28 09:52:48 +0100 | [diff] [blame] | 42 | /* Instruction patching registers */ |
| 43 | #define CPUPSELR_EL3 S3_6_C15_C8_0 |
| 44 | #define CPUPCR_EL3 S3_6_C15_C8_1 |
| 45 | #define CPUPOR_EL3 S3_6_C15_C8_2 |
| 46 | #define CPUPMR_EL3 S3_6_C15_C8_3 |
| 47 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 48 | #endif /* CORTEX_A55_H */ |