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Dan Handley9df48042015-03-19 18:58:55 +00001/*
David Cunado2e36de82017-01-19 10:26:16 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6#ifndef __ARM_DEF_H__
7#define __ARM_DEF_H__
8
Soby Mathewfec4eb72015-07-01 16:16:20 +01009#include <arch.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <common_def.h>
11#include <platform_def.h>
Juan Castillo9b265a82015-05-07 14:52:44 +010012#include <tbbr_img_def.h>
Scott Brandenbf404c02017-04-10 11:45:52 -070013#include <utils_def.h>
Antonio Nino Diaz719bf852017-02-23 17:22:58 +000014#include <xlat_tables_defs.h>
Dan Handley9df48042015-03-19 18:58:55 +000015
16
17/******************************************************************************
18 * Definitions common to all ARM standard platforms
19 *****************************************************************************/
20
Juan Castillo7d199412015-12-14 09:35:25 +000021/* Special value used to verify platform parameters from BL2 to BL31 */
Dan Handley9df48042015-03-19 18:58:55 +000022#define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
23
Soby Mathewa869de12015-05-08 10:18:59 +010024#define ARM_SYSTEM_COUNT 1
Dan Handley9df48042015-03-19 18:58:55 +000025
26#define ARM_CACHE_WRITEBACK_SHIFT 6
27
Soby Mathewfec4eb72015-07-01 16:16:20 +010028/*
29 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
30 * power levels have a 1:1 mapping with the MPIDR affinity levels.
31 */
32#define ARM_PWR_LVL0 MPIDR_AFFLVL0
33#define ARM_PWR_LVL1 MPIDR_AFFLVL1
Soby Mathewa869de12015-05-08 10:18:59 +010034#define ARM_PWR_LVL2 MPIDR_AFFLVL2
Soby Mathewfec4eb72015-07-01 16:16:20 +010035
36/*
37 * Macros for local power states in ARM platforms encoded by State-ID field
38 * within the power-state parameter.
39 */
40/* Local power state for power domains in Run state. */
41#define ARM_LOCAL_STATE_RUN 0
42/* Local power state for retention. Valid only for CPU power domains */
43#define ARM_LOCAL_STATE_RET 1
44/* Local power state for OFF/power-down. Valid for CPU and cluster power
45 domains */
46#define ARM_LOCAL_STATE_OFF 2
47
Dan Handley9df48042015-03-19 18:58:55 +000048/* Memory location options for TSP */
49#define ARM_TRUSTED_SRAM_ID 0
50#define ARM_TRUSTED_DRAM_ID 1
51#define ARM_DRAM_ID 2
52
53/* The first 4KB of Trusted SRAM are used as shared memory */
54#define ARM_TRUSTED_SRAM_BASE 0x04000000
55#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
56#define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
57
58/* The remaining Trusted SRAM is used to load the BL images */
59#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
60 ARM_SHARED_RAM_SIZE)
61#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
62 ARM_SHARED_RAM_SIZE)
63
64/*
65 * The top 16MB of DRAM1 is configured as secure access only using the TZC
66 * - SCP TZC DRAM: If present, DRAM reserved for SCP use
67 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
68 */
David Cunado2e36de82017-01-19 10:26:16 +000069#define ARM_TZC_DRAM1_SIZE ULL(0x01000000)
Dan Handley9df48042015-03-19 18:58:55 +000070
71#define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
72 ARM_DRAM1_SIZE - \
73 ARM_SCP_TZC_DRAM1_SIZE)
74#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
75#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
76 ARM_SCP_TZC_DRAM1_SIZE - 1)
77
78#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
79 ARM_DRAM1_SIZE - \
80 ARM_TZC_DRAM1_SIZE)
81#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \
82 ARM_SCP_TZC_DRAM1_SIZE)
83#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
84 ARM_AP_TZC_DRAM1_SIZE - 1)
85
Soby Mathew7e4d6652017-05-10 11:50:30 +010086/* Define the Access permissions for Secure peripherals to NS_DRAM */
87#if ARM_CRYPTOCELL_INTEG
88/*
89 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell.
90 * This is required by CryptoCell to authenticate BL33 which is loaded
91 * into the Non Secure DDR.
92 */
93#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD
94#else
95#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE
96#endif
97
Summer Qin9db8f2e2017-04-24 16:49:28 +010098#ifdef SPD_opteed
99/*
Jens Wiklanderae73b162017-08-24 15:39:09 +0200100 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
101 * load/authenticate the trusted os extra image. The first 512KB of
102 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
103 * for OPTEE is paged image which only include the paging part using
104 * virtual memory but without "init" data. OPTEE will copy the "init" data
105 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the
106 * extra image behind the "init" data.
Summer Qin9db8f2e2017-04-24 16:49:28 +0100107 */
Jens Wiklanderae73b162017-08-24 15:39:09 +0200108#define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \
109 ARM_AP_TZC_DRAM1_SIZE - \
110 ARM_OPTEE_PAGEABLE_LOAD_SIZE)
111#define ARM_OPTEE_PAGEABLE_LOAD_SIZE 0x400000
Summer Qin9db8f2e2017-04-24 16:49:28 +0100112#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \
113 ARM_OPTEE_PAGEABLE_LOAD_BASE, \
114 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \
115 MT_MEMORY | MT_RW | MT_SECURE)
116#endif /* SPD_opteed */
Dan Handley9df48042015-03-19 18:58:55 +0000117
118#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
119#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
120 ARM_TZC_DRAM1_SIZE)
121#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
122 ARM_NS_DRAM1_SIZE - 1)
123
David Cunado2e36de82017-01-19 10:26:16 +0000124#define ARM_DRAM1_BASE ULL(0x80000000)
125#define ARM_DRAM1_SIZE ULL(0x80000000)
Dan Handley9df48042015-03-19 18:58:55 +0000126#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
127 ARM_DRAM1_SIZE - 1)
128
David Cunado2e36de82017-01-19 10:26:16 +0000129#define ARM_DRAM2_BASE ULL(0x880000000)
Dan Handley9df48042015-03-19 18:58:55 +0000130#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
131#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
132 ARM_DRAM2_SIZE - 1)
133
134#define ARM_IRQ_SEC_PHY_TIMER 29
135
136#define ARM_IRQ_SEC_SGI_0 8
137#define ARM_IRQ_SEC_SGI_1 9
138#define ARM_IRQ_SEC_SGI_2 10
139#define ARM_IRQ_SEC_SGI_3 11
140#define ARM_IRQ_SEC_SGI_4 12
141#define ARM_IRQ_SEC_SGI_5 13
142#define ARM_IRQ_SEC_SGI_6 14
143#define ARM_IRQ_SEC_SGI_7 15
144
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000145/*
146 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
147 * terminology. On a GICv2 system or mode, the lists will be merged and treated
148 * as Group 0 interrupts.
149 */
150#define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \
151 ARM_IRQ_SEC_SGI_1, \
152 ARM_IRQ_SEC_SGI_2, \
153 ARM_IRQ_SEC_SGI_3, \
154 ARM_IRQ_SEC_SGI_4, \
155 ARM_IRQ_SEC_SGI_5, \
156 ARM_IRQ_SEC_SGI_7
157
158#define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \
159 ARM_IRQ_SEC_SGI_6
160
Dan Handley9df48042015-03-19 18:58:55 +0000161#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
162 ARM_SHARED_RAM_BASE, \
163 ARM_SHARED_RAM_SIZE, \
Juan Castillo2e86cb12016-01-13 15:01:09 +0000164 MT_DEVICE | MT_RW | MT_SECURE)
Dan Handley9df48042015-03-19 18:58:55 +0000165
166#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
167 ARM_NS_DRAM1_BASE, \
168 ARM_NS_DRAM1_SIZE, \
169 MT_MEMORY | MT_RW | MT_NS)
170
171#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
172 TSP_SEC_MEM_BASE, \
173 TSP_SEC_MEM_SIZE, \
174 MT_MEMORY | MT_RW | MT_SECURE)
175
David Wang0ba499f2016-03-07 11:02:57 +0800176#if ARM_BL31_IN_DRAM
177#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
178 BL31_BASE, \
179 PLAT_ARM_MAX_BL31_SIZE, \
180 MT_MEMORY | MT_RW | MT_SECURE)
181#endif
Dan Handley9df48042015-03-19 18:58:55 +0000182
183/*
184 * The number of regions like RO(code), coherent and data required by
185 * different BL stages which need to be mapped in the MMU.
186 */
187#if USE_COHERENT_MEM
188#define ARM_BL_REGIONS 3
189#else
190#define ARM_BL_REGIONS 2
191#endif
192
193#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
194 ARM_BL_REGIONS)
195
196/* Memory mapped Generic timer interfaces */
197#define ARM_SYS_CNTCTL_BASE 0x2a430000
198#define ARM_SYS_CNTREAD_BASE 0x2a800000
199#define ARM_SYS_TIMCTL_BASE 0x2a810000
200
201#define ARM_CONSOLE_BAUDRATE 115200
202
Juan Castillob6132f12015-10-06 14:01:35 +0100203/* Trusted Watchdog constants */
204#define ARM_SP805_TWDG_BASE 0x2a490000
205#define ARM_SP805_TWDG_CLK_HZ 32768
206/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
207 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */
208#define ARM_TWDG_TIMEOUT_SEC 128
209#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
210 ARM_TWDG_TIMEOUT_SEC)
211
Dan Handley9df48042015-03-19 18:58:55 +0000212/******************************************************************************
213 * Required platform porting definitions common to all ARM standard platforms
214 *****************************************************************************/
215
Antonio Nino Diazf6601042016-12-13 13:48:31 +0000216#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
217#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
Dan Handley9df48042015-03-19 18:58:55 +0000218
Soby Mathewfec4eb72015-07-01 16:16:20 +0100219/*
220 * This macro defines the deepest retention state possible. A higher state
221 * id will represent an invalid or a power down state.
222 */
223#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
224
225/*
226 * This macro defines the deepest power down states possible. Any state ID
227 * higher than this is invalid.
228 */
229#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
230
Dan Handley9df48042015-03-19 18:58:55 +0000231/*
232 * Some data must be aligned on the biggest cache line size in the platform.
233 * This is known only to the platform as it might have a combination of
234 * integrated and external caches.
235 */
236#define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT)
237
Dan Handley9df48042015-03-19 18:58:55 +0000238
239/*******************************************************************************
240 * BL1 specific defines.
241 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
242 * addresses.
243 ******************************************************************************/
244#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
245#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \
246 + PLAT_ARM_TRUSTED_ROM_SIZE)
247/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000248 * Put BL1 RW at the top of the Trusted SRAM.
Dan Handley9df48042015-03-19 18:58:55 +0000249 */
Dan Handley9df48042015-03-19 18:58:55 +0000250#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
251 ARM_BL_RAM_SIZE - \
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000252 PLAT_ARM_MAX_BL1_RW_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000253#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
254
255/*******************************************************************************
256 * BL2 specific defines.
257 ******************************************************************************/
dp-armcdd03cb2017-02-15 11:07:55 +0000258#if ARM_BL31_IN_DRAM || defined(AARCH32)
David Wang0ba499f2016-03-07 11:02:57 +0800259/*
dp-armcdd03cb2017-02-15 11:07:55 +0000260 * For AArch32 BL31 is not applicable.
261 * For AArch64 BL31 is loaded in the DRAM.
David Wang0ba499f2016-03-07 11:02:57 +0800262 * Put BL2 just below BL1.
263 */
264#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
265#define BL2_LIMIT BL1_RW_BASE
266#else
Dan Handley9df48042015-03-19 18:58:55 +0000267/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000268 * Put BL2 just below BL31.
Dan Handley9df48042015-03-19 18:58:55 +0000269 */
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000270#define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000271#define BL2_LIMIT BL31_BASE
David Wang0ba499f2016-03-07 11:02:57 +0800272#endif
Dan Handley9df48042015-03-19 18:58:55 +0000273
274/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000275 * BL31 specific defines.
Dan Handley9df48042015-03-19 18:58:55 +0000276 ******************************************************************************/
David Wang0ba499f2016-03-07 11:02:57 +0800277#if ARM_BL31_IN_DRAM
278/*
279 * Put BL31 at the bottom of TZC secured DRAM
280 */
281#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
282#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
283 PLAT_ARM_MAX_BL31_SIZE)
284#else
Dan Handley9df48042015-03-19 18:58:55 +0000285/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000286 * Put BL31 at the top of the Trusted SRAM.
Dan Handley9df48042015-03-19 18:58:55 +0000287 */
288#define BL31_BASE (ARM_BL_RAM_BASE + \
289 ARM_BL_RAM_SIZE - \
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000290 PLAT_ARM_MAX_BL31_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000291#define BL31_PROGBITS_LIMIT BL1_RW_BASE
292#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
David Wang0ba499f2016-03-07 11:02:57 +0800293#endif
Dan Handley9df48042015-03-19 18:58:55 +0000294
295/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000296 * BL32 specific defines.
Dan Handley9df48042015-03-19 18:58:55 +0000297 ******************************************************************************/
298/*
299 * On ARM standard platforms, the TSP can execute from Trusted SRAM,
300 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
301 * controller.
302 */
David Wang0ba499f2016-03-07 11:02:57 +0800303#if ARM_BL31_IN_DRAM
304# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \
305 PLAT_ARM_MAX_BL31_SIZE)
306# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \
307 PLAT_ARM_MAX_BL31_SIZE)
308# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \
309 PLAT_ARM_MAX_BL31_SIZE)
310# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
311 ARM_AP_TZC_DRAM1_SIZE)
312#elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
Dan Handley9df48042015-03-19 18:58:55 +0000313# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
314# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
315# define TSP_PROGBITS_LIMIT BL2_BASE
316# define BL32_BASE ARM_BL_RAM_BASE
317# define BL32_LIMIT BL31_BASE
318#elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
319# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE
320# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE
321# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
322# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
323 + (1 << 21))
324#elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
325# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
326# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
327# define BL32_BASE ARM_AP_TZC_DRAM1_BASE
328# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
329 ARM_AP_TZC_DRAM1_SIZE)
330#else
331# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
332#endif
333
Soby Mathew0d268dc2016-07-11 14:13:56 +0100334/* BL32 is mandatory in AArch32 */
335#ifndef AARCH32
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100336#ifdef SPD_none
337#undef BL32_BASE
338#endif /* SPD_none */
Soby Mathew0d268dc2016-07-11 14:13:56 +0100339#endif
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100340
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100341/*******************************************************************************
342 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
343 ******************************************************************************/
344#define BL2U_BASE BL2_BASE
Yatharth Kochar18dfb302016-11-22 11:06:03 +0000345#if ARM_BL31_IN_DRAM || defined(AARCH32)
346/*
347 * For AArch32 BL31 is not applicable.
348 * For AArch64 BL31 is loaded in the DRAM.
349 * BL2U extends up to BL1.
350 */
David Wang0ba499f2016-03-07 11:02:57 +0800351#define BL2U_LIMIT BL1_RW_BASE
352#else
Yatharth Kochar18dfb302016-11-22 11:06:03 +0000353/* BL2U extends up to BL31. */
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100354#define BL2U_LIMIT BL31_BASE
David Wang0ba499f2016-03-07 11:02:57 +0800355#endif
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100356#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
Yatharth Kocharf11b29a2016-02-01 11:04:46 +0000357#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000)
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100358
Dan Handley9df48042015-03-19 18:58:55 +0000359/*
360 * ID of the secure physical generic timer interrupt used by the TSP.
361 */
362#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
363
364
Vikram Kanigirid79214c2015-09-09 10:52:13 +0100365/*
366 * One cache line needed for bakery locks on ARM platforms
367 */
368#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
369
370
Dan Handley9df48042015-03-19 18:58:55 +0000371#endif /* __ARM_DEF_H__ */