Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 7 | #include <arch.h> |
| 8 | #include <assert.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 9 | #include <cci400.h> |
Vikram Kanigiri | 40d468c | 2014-12-23 01:00:22 +0000 | [diff] [blame] | 10 | #include <debug.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 11 | #include <mmio.h> |
Juan Castillo | 7f1f062 | 2014-09-09 09:49:23 +0100 | [diff] [blame] | 12 | #include <stdint.h> |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 13 | |
| 14 | #define MAX_CLUSTERS 2 |
| 15 | |
Juan Castillo | 7f1f062 | 2014-09-09 09:49:23 +0100 | [diff] [blame] | 16 | static uintptr_t cci_base_addr; |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 17 | static unsigned int cci_cluster_ix_to_iface[MAX_CLUSTERS]; |
| 18 | |
| 19 | |
Juan Castillo | 7f1f062 | 2014-09-09 09:49:23 +0100 | [diff] [blame] | 20 | void cci_init(uintptr_t cci_base, |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 21 | int slave_iface3_cluster_ix, |
| 22 | int slave_iface4_cluster_ix) |
| 23 | { |
| 24 | /* |
| 25 | * Check the passed arguments are valid. The cluster indices must be |
| 26 | * less than MAX_CLUSTERS, not the same as each other and at least one |
Sandrine Bailleux | 18e785f | 2015-10-02 08:51:17 +0100 | [diff] [blame] | 27 | * of them must refer to a valid cluster index. |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 28 | */ |
| 29 | assert(cci_base); |
| 30 | assert(slave_iface3_cluster_ix < MAX_CLUSTERS); |
| 31 | assert(slave_iface4_cluster_ix < MAX_CLUSTERS); |
| 32 | assert(slave_iface3_cluster_ix != slave_iface4_cluster_ix); |
| 33 | assert((slave_iface3_cluster_ix >= 0) || |
Sandrine Bailleux | 18e785f | 2015-10-02 08:51:17 +0100 | [diff] [blame] | 34 | (slave_iface4_cluster_ix >= 0)); |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 35 | |
Vikram Kanigiri | 40d468c | 2014-12-23 01:00:22 +0000 | [diff] [blame] | 36 | WARN("Please migrate to common cci driver, This driver will be" \ |
| 37 | " deprecated in future\n"); |
| 38 | |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 39 | cci_base_addr = cci_base; |
| 40 | if (slave_iface3_cluster_ix >= 0) |
| 41 | cci_cluster_ix_to_iface[slave_iface3_cluster_ix] = |
| 42 | SLAVE_IFACE3_OFFSET; |
| 43 | if (slave_iface4_cluster_ix >= 0) |
| 44 | cci_cluster_ix_to_iface[slave_iface4_cluster_ix] = |
| 45 | SLAVE_IFACE4_OFFSET; |
| 46 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 47 | |
| 48 | static inline unsigned long get_slave_iface_base(unsigned long mpidr) |
| 49 | { |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 50 | /* |
| 51 | * We assume the TF topology code allocates affinity instances |
| 52 | * consecutively from zero. |
| 53 | * It is a programming error if this is called without initializing |
| 54 | * the slave interface to use for this cluster. |
| 55 | */ |
| 56 | unsigned int cluster_id = |
| 57 | (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; |
| 58 | |
| 59 | assert(cluster_id < MAX_CLUSTERS); |
| 60 | assert(cci_cluster_ix_to_iface[cluster_id] != 0); |
| 61 | |
| 62 | return cci_base_addr + cci_cluster_ix_to_iface[cluster_id]; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 63 | } |
| 64 | |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 65 | void cci_enable_cluster_coherency(unsigned long mpidr) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 66 | { |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 67 | assert(cci_base_addr); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 68 | /* Enable Snoops and DVM messages */ |
| 69 | mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG, |
| 70 | DVM_EN_BIT | SNOOP_EN_BIT); |
| 71 | |
| 72 | /* Wait for the dust to settle down */ |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 73 | while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT) |
Dan Handley | a70615f | 2014-04-09 12:48:25 +0100 | [diff] [blame] | 74 | ; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 75 | } |
| 76 | |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 77 | void cci_disable_cluster_coherency(unsigned long mpidr) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 78 | { |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 79 | assert(cci_base_addr); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 80 | /* Disable Snoops and DVM messages */ |
| 81 | mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG, |
| 82 | ~(DVM_EN_BIT | SNOOP_EN_BIT)); |
| 83 | |
| 84 | /* Wait for the dust to settle down */ |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 85 | while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT) |
Dan Handley | a70615f | 2014-04-09 12:48:25 +0100 | [diff] [blame] | 86 | ; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 87 | } |
| 88 | |