| developer | 8015906 | 2021-11-08 16:37:39 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef APUPWR_CLKCTL_DEF_H |
| 8 | #define APUPWR_CLKCTL_DEF_H |
| 9 | |
| 10 | #include <lib/mmio.h> |
| 11 | |
| 12 | enum dvfs_voltage_domain { |
| 13 | V_VPU0 = 0, |
| 14 | V_VPU1 = 1, |
| 15 | V_MDLA0 = 2, |
| 16 | V_MDLA1 = 3, |
| 17 | V_APU_CONN = 4, |
| 18 | V_TOP_IOMMU = 5, |
| 19 | V_VCORE = 6, |
| 20 | APUSYS_BUCK_DOMAIN_NUM = 7, |
| 21 | }; |
| 22 | |
| 23 | enum dvfs_freq { |
| 24 | DVFS_FREQ_NOT_SUPPORT = 0, |
| 25 | DVFS_FREQ_ACC_26M = 1, |
| 26 | DVFS_FREQ_ACC_PARKING = 2, |
| 27 | DVFS_FREQ_ACC_SOC = 3, |
| 28 | DVFS_FREQ_ACC_APUPLL = 4, |
| 29 | DVFS_FREQ_00_026000_F = 26000, |
| 30 | DVFS_FREQ_00_208000_F = 208000, |
| 31 | DVFS_FREQ_00_238000_F = 238000, |
| 32 | DVFS_FREQ_00_273000_F = 273000, |
| 33 | DVFS_FREQ_00_312000_F = 312000, |
| 34 | DVFS_FREQ_00_358000_F = 358000, |
| 35 | DVFS_FREQ_00_385000_F = 385000, |
| 36 | DVFS_FREQ_00_499200_F = 499200, |
| 37 | DVFS_FREQ_00_500000_F = 500000, |
| 38 | DVFS_FREQ_00_525000_F = 525000, |
| 39 | DVFS_FREQ_00_546000_F = 546000, |
| 40 | DVFS_FREQ_00_594000_F = 594000, |
| 41 | DVFS_FREQ_00_624000_F = 624000, |
| 42 | DVFS_FREQ_00_688000_F = 688000, |
| 43 | DVFS_FREQ_00_687500_F = 687500, |
| 44 | DVFS_FREQ_00_728000_F = 728000, |
| 45 | DVFS_FREQ_00_800000_F = 800000, |
| 46 | DVFS_FREQ_00_832000_F = 832000, |
| 47 | DVFS_FREQ_00_960000_F = 960000, |
| 48 | DVFS_FREQ_00_1100000_F = 1100000, |
| 49 | }; |
| 50 | #define DVFS_FREQ_MAX (DVFS_FREQ_00_1100000_F) |
| 51 | |
| 52 | enum pll_set_rate_mode { |
| 53 | CON0_PCW = 0, |
| 54 | FHCTL_SW = 1, |
| 55 | FHCTL_HW = 2, |
| 56 | PLL_SET_RATE_MODE_MAX = 3, |
| 57 | }; |
| 58 | |
| 59 | enum apupll { |
| 60 | APUPLL = 0, |
| 61 | NPUPLL = 1, |
| 62 | APUPLL1 = 2, |
| 63 | APUPLL2 = 3, |
| 64 | APUPLL_MAX = 4, |
| 65 | }; |
| 66 | |
| 67 | #define BUCK_VVPU_DOMAIN_DEFAULT_FREQ (DVFS_FREQ_00_273000_F) |
| 68 | #define BUCK_VMDLA_DOMAIN_DEFAULT_FREQ (DVFS_FREQ_00_312000_F) |
| 69 | #define BUCK_VCONN_DOMAIN_DEFAULT_FREQ (DVFS_FREQ_00_208000_F) |
| 70 | |
| 71 | #define apupwr_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) |
| 72 | #define apupwr_writel_relax(VAL, REG) mmio_write_32_relax((uintptr_t)REG, VAL) |
| 73 | #define apupwr_readl(REG) mmio_read_32((uintptr_t)REG) |
| 74 | #define apupwr_clrbits(VAL, REG) mmio_clrbits_32((uintptr_t)REG, VAL) |
| 75 | #define apupwr_setbits(VAL, REG) mmio_setbits_32((uintptr_t)REG, VAL) |
| 76 | #define apupwr_clrsetbits(CLR_VAL, SET_VAL, REG) \ |
| 77 | mmio_clrsetbits_32((uintptr_t)REG, CLR_VAL, SET_VAL) |
| 78 | |
| 79 | /* PLL and related register */ |
| 80 | #define APU_PLL_BASE (APUSYS_APU_PLL_BASE) |
| 81 | #define APU_PLL4H_PLL1_CON0 (APU_PLL_BASE + 0x008) |
| 82 | #define APU_PLL4H_PLL1_CON1 (APU_PLL_BASE + 0x00C) |
| 83 | #define APU_PLL4H_PLL1_CON3 (APU_PLL_BASE + 0x014) |
| 84 | |
| 85 | #define APU_PLL4H_PLL2_CON0 (APU_PLL_BASE + 0x018) |
| 86 | #define APU_PLL4H_PLL2_CON1 (APU_PLL_BASE + 0x01C) |
| 87 | #define APU_PLL4H_PLL2_CON3 (APU_PLL_BASE + 0x024) |
| 88 | |
| 89 | #define APU_PLL4H_PLL3_CON0 (APU_PLL_BASE + 0x028) |
| 90 | #define APU_PLL4H_PLL3_CON1 (APU_PLL_BASE + 0x02C) |
| 91 | #define APU_PLL4H_PLL3_CON3 (APU_PLL_BASE + 0x034) |
| 92 | |
| 93 | #define APU_PLL4H_PLL4_CON0 (APU_PLL_BASE + 0x038) |
| 94 | #define APU_PLL4H_PLL4_CON1 (APU_PLL_BASE + 0x03C) |
| 95 | #define APU_PLL4H_PLL4_CON3 (APU_PLL_BASE + 0x044) |
| 96 | |
| 97 | #define APU_PLL4H_FHCTL_HP_EN (APU_PLL_BASE + 0x0E00) |
| 98 | #define APU_PLL4H_FHCTL_UNITSLOPE_EN (APU_PLL_BASE + 0x0E04) |
| 99 | #define APU_PLL4H_FHCTL_CLK_CON (APU_PLL_BASE + 0x0E08) |
| 100 | #define APU_PLL4H_FHCTL_RST_CON (APU_PLL_BASE + 0x0E0C) |
| 101 | #define APU_PLL4H_FHCTL_SLOPE0 (APU_PLL_BASE + 0x0E10) |
| 102 | #define APU_PLL4H_FHCTL_SLOPE1 (APU_PLL_BASE + 0x0E14) |
| 103 | #define APU_PLL4H_FHCTL_DSSC_CFG (APU_PLL_BASE + 0x0E18) |
| 104 | #define APU_PLL4H_FHCTL_DSSC0_CON (APU_PLL_BASE + 0x0E1C) |
| 105 | #define APU_PLL4H_FHCTL_DSSC1_CON (APU_PLL_BASE + 0x0E20) |
| 106 | #define APU_PLL4H_FHCTL_DSSC2_CON (APU_PLL_BASE + 0x0E24) |
| 107 | #define APU_PLL4H_FHCTL_DSSC3_CON (APU_PLL_BASE + 0x0E28) |
| 108 | #define APU_PLL4H_FHCTL_DSSC4_CON (APU_PLL_BASE + 0x0E2C) |
| 109 | #define APU_PLL4H_FHCTL_DSSC5_CON (APU_PLL_BASE + 0x0E30) |
| 110 | #define APU_PLL4H_FHCTL_DSSC6_CON (APU_PLL_BASE + 0x0E34) |
| 111 | #define APU_PLL4H_FHCTL_DSSC7_CON (APU_PLL_BASE + 0x0E38) |
| 112 | #define APU_PLL4H_FHCTL0_CFG (APU_PLL_BASE + 0x0E3C) |
| 113 | #define APU_PLL4H_FHCTL0_UPDNLMT (APU_PLL_BASE + 0x0E40) |
| 114 | #define APU_PLL4H_FHCTL0_DDS (APU_PLL_BASE + 0x0E44) |
| 115 | #define APU_PLL4H_FHCTL0_DVFS (APU_PLL_BASE + 0x0E48) |
| 116 | #define APU_PLL4H_FHCTL0_MON (APU_PLL_BASE + 0x0E4C) |
| 117 | #define APU_PLL4H_FHCTL1_CFG (APU_PLL_BASE + 0x0E50) |
| 118 | #define APU_PLL4H_FHCTL1_UPDNLMT (APU_PLL_BASE + 0x0E54) |
| 119 | #define APU_PLL4H_FHCTL1_DDS (APU_PLL_BASE + 0x0E58) |
| 120 | #define APU_PLL4H_FHCTL1_DVFS (APU_PLL_BASE + 0x0E5C) |
| 121 | #define APU_PLL4H_FHCTL1_MON (APU_PLL_BASE + 0x0E60) |
| 122 | #define APU_PLL4H_FHCTL2_CFG (APU_PLL_BASE + 0x0E64) |
| 123 | #define APU_PLL4H_FHCTL2_UPDNLMT (APU_PLL_BASE + 0x0E68) |
| 124 | #define APU_PLL4H_FHCTL2_DDS (APU_PLL_BASE + 0x0E6C) |
| 125 | #define APU_PLL4H_FHCTL2_DVFS (APU_PLL_BASE + 0x0E70) |
| 126 | #define APU_PLL4H_FHCTL2_MON (APU_PLL_BASE + 0x0E74) |
| 127 | #define APU_PLL4H_FHCTL3_CFG (APU_PLL_BASE + 0x0E78) |
| 128 | #define APU_PLL4H_FHCTL3_UPDNLMT (APU_PLL_BASE + 0x0E7C) |
| 129 | #define APU_PLL4H_FHCTL3_DDS (APU_PLL_BASE + 0x0E80) |
| 130 | #define APU_PLL4H_FHCTL3_DVFS (APU_PLL_BASE + 0x0E84) |
| 131 | #define APU_PLL4H_FHCTL3_MON (APU_PLL_BASE + 0x0E88) |
| 132 | |
| 133 | /* PLL4H_PLLx_CON0 */ |
| 134 | #define RG_PLL_EN BIT(0) |
| 135 | |
| 136 | /* PLL4H_PLLx_CON1 */ |
| 137 | #define RG_PLL_SDM_PCW_CHG BIT(31) |
| 138 | #define POSDIV_SHIFT (24U) |
| 139 | #define POSDIV_MASK (0x7) |
| 140 | |
| 141 | /* PLL4H_PLLx_CON3 */ |
| 142 | #define DA_PLL_SDM_PWR_ON BIT(0) |
| 143 | #define DA_PLL_SDM_ISO_EN BIT(1) |
| 144 | |
| 145 | /* FHCTLx_DDS */ |
| 146 | #define DDS_MASK GENMASK_32(21, 0) |
| 147 | #define PCW_FRACTIONAL_SHIFT 14U |
| 148 | #define PLL_TGL_ORG BIT(31) |
| 149 | |
| 150 | #define PLL_READY_TIME_20US (20U) |
| 151 | #define PLL_CMD_READY_TIME_1US (1U) |
| 152 | |
| 153 | #define FREQ_VCO_MIN (1500U) /* 1500MHz*/ |
| 154 | #define FREQ_FIN (26U) /* 26M*/ |
| 155 | |
| 156 | /* ACC and related register */ |
| 157 | #define APU_ACC_BASE (APUSYS_APU_ACC_BASE) |
| 158 | #define APU_ACC_CONFG_SET0 (APU_ACC_BASE + 0x000) |
| 159 | #define APU_ACC_CONFG_SET1 (APU_ACC_BASE + 0x004) |
| 160 | #define APU_ACC_CONFG_SET2 (APU_ACC_BASE + 0x008) |
| 161 | #define APU_ACC_CONFG_SET4 (APU_ACC_BASE + 0x010) |
| 162 | #define APU_ACC_CONFG_SET5 (APU_ACC_BASE + 0x014) |
| 163 | #define APU_ACC_CONFG_SET7 (APU_ACC_BASE + 0x01C) |
| 164 | |
| 165 | #define APU_ACC_CONFG_CLR0 (APU_ACC_BASE + 0x040) |
| 166 | #define APU_ACC_CONFG_CLR1 (APU_ACC_BASE + 0x044) |
| 167 | #define APU_ACC_CONFG_CLR2 (APU_ACC_BASE + 0x048) |
| 168 | #define APU_ACC_CONFG_CLR4 (APU_ACC_BASE + 0x050) |
| 169 | #define APU_ACC_CONFG_CLR5 (APU_ACC_BASE + 0x054) |
| 170 | #define APU_ACC_CONFG_CLR7 (APU_ACC_BASE + 0x05C) |
| 171 | |
| 172 | #define APU_ACC_FM_CONFG_SET (APU_ACC_BASE + 0x0C0) |
| 173 | #define APU_ACC_FM_CONFG_CLR (APU_ACC_BASE + 0x0C4) |
| 174 | #define APU_ACC_FM_SEL (APU_ACC_BASE + 0x0C8) |
| 175 | #define APU_ACC_FM_CNT (APU_ACC_BASE + 0x0CC) |
| 176 | |
| 177 | /* APU AO control */ |
| 178 | #define APU_AO_CTRL_BASE (APUSYS_APU_S_S_4_BASE) |
| 179 | #define APU_CSR_DUMMY_0 (APU_AO_CTRL_BASE + 0x24) |
| 180 | |
| 181 | #define AO_MD32_MNOC_MASK (BIT(1) | BIT(0)) |
| 182 | |
| 183 | #define BIT_CGEN_F26M (0) |
| 184 | #define BIT_CGEN_PARK (1) |
| 185 | #define BIT_CGEN_SOC (2) |
| 186 | #define BIT_CGEN_APU (3) |
| 187 | #define BIT_CGEN_OUT (4) |
| 188 | #define BIT_SEL_PARK (8) |
| 189 | #define BIT_SEL_F26M (9) |
| 190 | #define BIT_SEL_APU_DIV2 (10) |
| 191 | #define BIT_SEL_APU (11) |
| 192 | #define BIT_SEL_PARK_SRC_OUT (12) |
| 193 | #define BIT_INVEN_OUT (15) |
| 194 | |
| 195 | #endif /* APUPWR_CLKCTL_DEF_H*/ |