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Deepak Pandey9cbacf62018-08-08 10:32:51 +05301/*
sah016ec01e82021-06-06 14:38:01 +05302 * Copyright (c) 2018-2022, Arm Limited. All rights reserved.
Deepak Pandey9cbacf62018-08-08 10:32:51 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Max Shvetsov0ac39412019-11-19 11:01:26 +00007#include <common/debug.h>
Antonio Nino Diaz1b0c6f12019-01-23 21:08:43 +00008#include <drivers/arm/css/css_mhu_doorbell.h>
Antonio Nino Diazc30db5b2019-01-23 20:37:32 +00009#include <drivers/arm/css/scmi.h>
Manoj Kumar69bebd82019-06-21 17:07:13 +010010#include <drivers/arm/css/sds.h>
Manish Pandey2c44a442019-10-14 17:37:38 +010011#include <drivers/arm/gic600_multichip.h>
Manoj Kumar69bebd82019-06-21 17:07:13 +010012#include <lib/mmio.h>
13#include <lib/utils.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000014#include <plat/arm/common/plat_arm.h>
15
Manoj Kumar69bebd82019-06-21 17:07:13 +010016#include "n1sdp_def.h"
sah016ec01e82021-06-06 14:38:01 +053017#include <platform_def.h>
Manoj Kumar69bebd82019-06-21 17:07:13 +010018
19/*
Manish Pandey2f3203f2019-10-07 17:47:46 +010020 * Platform information structure stored in SDS.
21 * This structure holds information about platform's DDR
22 * size which will be used to zero out the memory before
23 * enabling the ECC capability as well as information
24 * about multichip setup
25 * - multichip mode
sah016ec01e82021-06-06 14:38:01 +053026 * - secondary_count
Manish Pandey2f3203f2019-10-07 17:47:46 +010027 * - Local DDR size in GB, DDR memory in master board
sah016ec01e82021-06-06 14:38:01 +053028 * - Remote DDR size in GB, DDR memory in secondary board
Manoj Kumar69bebd82019-06-21 17:07:13 +010029 */
Manish Pandey2f3203f2019-10-07 17:47:46 +010030struct n1sdp_plat_info {
31 bool multichip_mode;
sah016ec01e82021-06-06 14:38:01 +053032 uint8_t secondary_count;
Manish Pandey2f3203f2019-10-07 17:47:46 +010033 uint8_t local_ddr_size;
34 uint8_t remote_ddr_size;
35} __packed;
Manoj Kumar69bebd82019-06-21 17:07:13 +010036
Deepak Pandey9cbacf62018-08-08 10:32:51 +053037static scmi_channel_plat_info_t n1sdp_scmi_plat_info = {
Manish Pandey2f3203f2019-10-07 17:47:46 +010038 .scmi_mbx_mem = N1SDP_SCMI_PAYLOAD_BASE,
39 .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
40 .db_preserve_mask = 0xfffffffe,
41 .db_modify_mask = 0x1,
42 .ring_doorbell = &mhu_ring_doorbell
Deepak Pandey9cbacf62018-08-08 10:32:51 +053043};
44
Manish Pandey2c44a442019-10-14 17:37:38 +010045static struct gic600_multichip_data n1sdp_multichip_data __init = {
46 .rt_owner_base = PLAT_ARM_GICD_BASE,
47 .rt_owner = 0,
48 .chip_count = 1,
49 .chip_addrs = {
50 PLAT_ARM_GICD_BASE >> 16,
51 PLAT_ARM_GICD_BASE >> 16
52 },
53 .spi_ids = {
Sayanta Pattanayakfcf68522020-07-31 12:59:24 +053054 {32, 479},
55 {512, 959}
Manish Pandey2c44a442019-10-14 17:37:38 +010056 }
57};
58
59static uintptr_t n1sdp_multichip_gicr_frames[3] = {
60 PLAT_ARM_GICR_BASE,
61 PLAT_ARM_GICR_BASE + PLAT_ARM_REMOTE_CHIP_OFFSET,
62 0
63};
64
Aditya Angadi7f8837b2019-12-31 14:23:53 +053065scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
Deepak Pandey9cbacf62018-08-08 10:32:51 +053066{
67 return &n1sdp_scmi_plat_info;
68}
Chandni Cherukurie4bf6a02018-11-14 13:43:59 +053069
70const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
71{
72 return css_scmi_override_pm_ops(ops);
73}
Manoj Kumar69bebd82019-06-21 17:07:13 +010074
75/*
76 * N1SDP platform supports RDIMMs with ECC capability. To use the ECC
77 * capability, the entire DDR memory space has to be zeroed out before
78 * enabling the ECC bits in DMC620. Zeroing out several gigabytes of
79 * memory from SCP is quite time consuming so the following function
80 * is added to zero out the DDR memory from application processor which is
sah016ec01e82021-06-06 14:38:01 +053081 * much faster compared to SCP. Local DDR memory is zeroed out during BL2
82 * stage. If remote chip is connected, it's DDR memory is zeroed out here.
Manoj Kumar69bebd82019-06-21 17:07:13 +010083 */
84
Manish Pandeyb68e2862019-09-11 17:07:40 +010085void remote_dmc_ecc_setup(uint8_t remote_ddr_size)
86{
87 uint64_t remote_dram2_size;
88
89 remote_dram2_size = (remote_ddr_size * 1024UL * 1024UL * 1024UL) -
90 N1SDP_REMOTE_DRAM1_SIZE;
91 /* multichip setup */
92 INFO("Zeroing remote DDR memories\n");
93 zero_normalmem((void *)N1SDP_REMOTE_DRAM1_BASE,
94 N1SDP_REMOTE_DRAM1_SIZE);
95 flush_dcache_range(N1SDP_REMOTE_DRAM1_BASE, N1SDP_REMOTE_DRAM1_SIZE);
96 zero_normalmem((void *)N1SDP_REMOTE_DRAM2_BASE, remote_dram2_size);
97 flush_dcache_range(N1SDP_REMOTE_DRAM2_BASE, remote_dram2_size);
98
99 INFO("Enabling ECC on remote DMCs\n");
100 /* Set DMCs to CONFIG state before writing ERR0CTLR0 register */
101 mmio_write_32(N1SDP_REMOTE_DMC0_MEMC_CMD_REG,
102 N1SDP_DMC_MEMC_CMD_CONFIG);
103 mmio_write_32(N1SDP_REMOTE_DMC1_MEMC_CMD_REG,
104 N1SDP_DMC_MEMC_CMD_CONFIG);
105
106 /* Enable ECC in DMCs */
107 mmio_setbits_32(N1SDP_REMOTE_DMC0_ERR0CTLR0_REG,
108 N1SDP_DMC_ERR0CTLR0_ECC_EN);
109 mmio_setbits_32(N1SDP_REMOTE_DMC1_ERR0CTLR0_REG,
110 N1SDP_DMC_ERR0CTLR0_ECC_EN);
111
112 /* Set DMCs to READY state */
113 mmio_write_32(N1SDP_REMOTE_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
114 mmio_write_32(N1SDP_REMOTE_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY);
115}
116
Manish Pandey2c44a442019-10-14 17:37:38 +0100117void n1sdp_bl31_multichip_setup(void)
118{
119 plat_arm_override_gicr_frames(n1sdp_multichip_gicr_frames);
120 gic600_multichip_init(&n1sdp_multichip_data);
121}
122
Manoj Kumar69bebd82019-06-21 17:07:13 +0100123void bl31_platform_setup(void)
124{
125 int ret;
Manish Pandey2f3203f2019-10-07 17:47:46 +0100126 struct n1sdp_plat_info plat_info;
Manoj Kumar69bebd82019-06-21 17:07:13 +0100127
Manoj Kumar69bebd82019-06-21 17:07:13 +0100128 ret = sds_init();
129 if (ret != SDS_OK) {
130 ERROR("SDS initialization failed\n");
131 panic();
132 }
133
Manish Pandey2f3203f2019-10-07 17:47:46 +0100134 ret = sds_struct_read(N1SDP_SDS_PLATFORM_INFO_STRUCT_ID,
135 N1SDP_SDS_PLATFORM_INFO_OFFSET,
136 &plat_info,
137 N1SDP_SDS_PLATFORM_INFO_SIZE,
Manoj Kumar69bebd82019-06-21 17:07:13 +0100138 SDS_ACCESS_MODE_NON_CACHED);
139 if (ret != SDS_OK) {
Manish Pandey2f3203f2019-10-07 17:47:46 +0100140 ERROR("Error getting platform info from SDS\n");
141 panic();
142 }
143 /* Validate plat_info SDS */
144 if ((plat_info.local_ddr_size == 0)
145 || (plat_info.local_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB)
146 || (plat_info.remote_ddr_size > N1SDP_MAX_DDR_CAPACITY_GB)
sah016ec01e82021-06-06 14:38:01 +0530147 || (plat_info.secondary_count > N1SDP_MAX_SECONDARY_COUNT)) {
Manish Pandey2f3203f2019-10-07 17:47:46 +0100148 ERROR("platform info SDS is corrupted\n");
Manoj Kumar69bebd82019-06-21 17:07:13 +0100149 panic();
150 }
Manish Pandey2f3203f2019-10-07 17:47:46 +0100151
Manish Pandey2c44a442019-10-14 17:37:38 +0100152 if (plat_info.multichip_mode) {
sah016ec01e82021-06-06 14:38:01 +0530153 n1sdp_multichip_data.chip_count = plat_info.secondary_count + 1;
Manish Pandey2c44a442019-10-14 17:37:38 +0100154 n1sdp_bl31_multichip_setup();
155 }
156 arm_bl31_platform_setup();
157
Manish Pandeyb68e2862019-09-11 17:07:40 +0100158 /* Check if remote memory is present */
159 if ((plat_info.multichip_mode) && (plat_info.remote_ddr_size != 0))
160 remote_dmc_ecc_setup(plat_info.remote_ddr_size);
Manoj Kumar69bebd82019-06-21 17:07:13 +0100161}