Manish V Badarkhe | 8a76603 | 2022-02-23 11:26:53 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022 Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * |
| 6 | * DRTM service |
| 7 | * |
| 8 | * Authors: |
| 9 | * Lucian Paul-Trifu <lucian.paultrifu@gmail.com> |
| 10 | * Brian Nezvadovitz <brinez@microsoft.com> 2021-02-01 |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #ifndef ARM_DRTM_SVC_H |
| 15 | #define ARM_DRTM_SVC_H |
| 16 | |
| 17 | /* |
| 18 | * SMC function IDs for DRTM Service |
| 19 | * Upper word bits set: Fast call, SMC64, Standard Secure Svc. Call (OEN = 4) |
| 20 | */ |
| 21 | #define DRTM_FID(func_num) \ |
| 22 | ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \ |
| 23 | (SMC_64 << FUNCID_CC_SHIFT) | \ |
| 24 | (OEN_STD_START << FUNCID_OEN_SHIFT) | \ |
| 25 | ((func_num) << FUNCID_NUM_SHIFT)) |
| 26 | |
| 27 | #define DRTM_FNUM_SVC_VERSION U(0x110) |
| 28 | #define DRTM_FNUM_SVC_FEATURES U(0x111) |
| 29 | #define DRTM_FNUM_SVC_UNPROTECT_MEM U(0x113) |
| 30 | #define DRTM_FNUM_SVC_DYNAMIC_LAUNCH U(0x114) |
| 31 | #define DRTM_FNUM_SVC_CLOSE_LOCALITY U(0x115) |
| 32 | #define DRTM_FNUM_SVC_GET_ERROR U(0x116) |
| 33 | #define DRTM_FNUM_SVC_SET_ERROR U(0x117) |
| 34 | #define DRTM_FNUM_SVC_SET_TCB_HASH U(0x118) |
| 35 | #define DRTM_FNUM_SVC_LOCK_TCB_HASH U(0x119) |
| 36 | |
| 37 | #define ARM_DRTM_SVC_VERSION DRTM_FID(DRTM_FNUM_SVC_VERSION) |
| 38 | #define ARM_DRTM_SVC_FEATURES DRTM_FID(DRTM_FNUM_SVC_FEATURES) |
| 39 | #define ARM_DRTM_SVC_UNPROTECT_MEM DRTM_FID(DRTM_FNUM_SVC_UNPROTECT_MEM) |
| 40 | #define ARM_DRTM_SVC_DYNAMIC_LAUNCH DRTM_FID(DRTM_FNUM_SVC_DYNAMIC_LAUNCH) |
| 41 | #define ARM_DRTM_SVC_CLOSE_LOCALITY DRTM_FID(DRTM_FNUM_SVC_CLOSE_LOCALITY) |
| 42 | #define ARM_DRTM_SVC_GET_ERROR DRTM_FID(DRTM_FNUM_SVC_GET_ERROR) |
| 43 | #define ARM_DRTM_SVC_SET_ERROR DRTM_FID(DRTM_FNUM_SVC_SET_ERROR) |
| 44 | #define ARM_DRTM_SVC_SET_TCB_HASH DRTM_FID(DRTM_FNUM_SVC_SET_TCB_HASH) |
| 45 | #define ARM_DRTM_SVC_LOCK_TCB_HASH DRTM_FID(DRTM_FNUM_SVC_LOCK_TCB_HASH) |
| 46 | |
| 47 | #define is_drtm_fid(_fid) \ |
| 48 | (((_fid) >= ARM_DRTM_SVC_VERSION) && ((_fid) <= ARM_DRTM_SVC_LOCK_TCB_HASH)) |
| 49 | |
| 50 | /* ARM DRTM Service Calls version numbers */ |
| 51 | #define ARM_DRTM_VERSION_MAJOR U(0) |
| 52 | #define ARM_DRTM_VERSION_MAJOR_SHIFT 16 |
| 53 | #define ARM_DRTM_VERSION_MAJOR_MASK U(0x7FFF) |
| 54 | #define ARM_DRTM_VERSION_MINOR U(1) |
| 55 | #define ARM_DRTM_VERSION_MINOR_SHIFT 0 |
| 56 | #define ARM_DRTM_VERSION_MINOR_MASK U(0xFFFF) |
| 57 | |
| 58 | #define ARM_DRTM_VERSION \ |
| 59 | ((((ARM_DRTM_VERSION_MAJOR) & ARM_DRTM_VERSION_MAJOR_MASK) << \ |
| 60 | ARM_DRTM_VERSION_MAJOR_SHIFT) \ |
| 61 | | (((ARM_DRTM_VERSION_MINOR) & ARM_DRTM_VERSION_MINOR_MASK) << \ |
| 62 | ARM_DRTM_VERSION_MINOR_SHIFT)) |
| 63 | |
| 64 | #define ARM_DRTM_FUNC_SHIFT U(63) |
| 65 | #define ARM_DRTM_FUNC_MASK U(0x1) |
| 66 | #define ARM_DRTM_FUNC_ID U(0x0) |
| 67 | #define ARM_DRTM_FEAT_ID U(0x1) |
| 68 | |
johpow01 | baa3e6c | 2022-03-11 17:50:58 -0600 | [diff] [blame^] | 69 | /* |
| 70 | * Definitions for DRTM features as per DRTM beta0 section 3.3, |
| 71 | * Table 6 DRTM_FEATURES |
| 72 | */ |
| 73 | #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT U(33) |
| 74 | #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK ULL(0xF) |
| 75 | #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_DEFAULT ULL(0x1) |
| 76 | |
| 77 | #define ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT U(32) |
| 78 | #define ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK ULL(0x1) |
| 79 | #define ARM_DRTM_TPM_FEATURES_TPM_HASH_NOT_SUPPORTED ULL(0x0) |
| 80 | #define ARM_DRTM_TPM_FEATURES_TPM_HASH_SUPPORTED ULL(0x1) |
| 81 | |
| 82 | #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT U(0) |
| 83 | #define ARM_DRTM_TPM_FEATURES_FW_HASH_MASK ULL(0xFFFFFFFF) |
| 84 | #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA256 ULL(0xB) |
| 85 | #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA384 ULL(0xC) |
| 86 | #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA512 ULL(0xD) |
| 87 | |
| 88 | #define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT U(32) |
| 89 | #define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK ULL(0xFFFFFFFF) |
| 90 | |
| 91 | #define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT U(0) |
| 92 | #define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK ULL(0xFFFFFFFF) |
| 93 | |
| 94 | #define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT U(8) |
| 95 | #define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK ULL(0xF) |
| 96 | |
| 97 | #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT U(0) |
| 98 | #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK ULL(0xFF) |
| 99 | #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_COMPLETE ULL(0x1) |
| 100 | #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_REGION ULL(0x2) |
| 101 | |
| 102 | #define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT U(0) |
| 103 | #define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK ULL(0xFF) |
| 104 | |
| 105 | #define ARM_DRTM_TPM_FEATURES_SET_PCR_SCHEMA(reg, val) \ |
| 106 | do { \ |
| 107 | reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK \ |
| 108 | << ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT)) | (((val) & \ |
| 109 | ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK) << \ |
| 110 | ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT)); \ |
| 111 | } while (false) |
| 112 | |
| 113 | #define ARM_DRTM_TPM_FEATURES_SET_TPM_HASH(reg, val) \ |
| 114 | do { \ |
| 115 | reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK \ |
| 116 | << ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT)) | (((val) & \ |
| 117 | ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK) << \ |
| 118 | ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT)); \ |
| 119 | } while (false) |
| 120 | |
| 121 | #define ARM_DRTM_TPM_FEATURES_SET_FW_HASH(reg, val) \ |
| 122 | do { \ |
| 123 | reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_FW_HASH_MASK \ |
| 124 | << ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT)) | (((val) & \ |
| 125 | ARM_DRTM_TPM_FEATURES_FW_HASH_MASK) << \ |
| 126 | ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT)); \ |
| 127 | } while (false) |
| 128 | |
| 129 | #define ARM_DRTM_MIN_MEM_REQ_SET_DCE_SIZE(reg, val) \ |
| 130 | do { \ |
| 131 | reg = (((reg) & ~(ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK \ |
| 132 | << ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT)) | (((val) & \ |
| 133 | ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK) << \ |
| 134 | ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT)); \ |
| 135 | } while (false) |
| 136 | |
| 137 | #define ARM_DRTM_MIN_MEM_REQ_SET_MIN_DLME_DATA_SIZE(reg, val) \ |
| 138 | do { \ |
| 139 | reg = (((reg) & \ |
| 140 | ~(ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK << \ |
| 141 | ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT)) | \ |
| 142 | (((val) & ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK) \ |
| 143 | << ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT)); \ |
| 144 | } while (false) |
| 145 | |
| 146 | #define ARM_DRTM_DMA_PROT_FEATURES_SET_MAX_REGIONS(reg, val) \ |
| 147 | do { \ |
| 148 | reg = (((reg) & \ |
| 149 | ~(ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK << \ |
| 150 | ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT)) | \ |
| 151 | (((val) & ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK) \ |
| 152 | << ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT)); \ |
| 153 | } while (false) |
| 154 | |
| 155 | #define ARM_DRTM_DMA_PROT_FEATURES_SET_DMA_SUPPORT(reg, val) \ |
| 156 | do { \ |
| 157 | reg = (((reg) & \ |
| 158 | ~(ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK << \ |
| 159 | ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT)) | \ |
| 160 | (((val) & ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK) \ |
| 161 | << ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT)); \ |
| 162 | } while (false) |
| 163 | |
| 164 | #define ARM_DRTM_TCB_HASH_FEATURES_SET_MAX_NUM_HASHES(reg, val) \ |
| 165 | do { \ |
| 166 | reg = (((reg) & \ |
| 167 | ~(ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK << \ |
| 168 | ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT)) | \ |
| 169 | (((val) & \ |
| 170 | ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK) << \ |
| 171 | ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT)); \ |
| 172 | } while (false) |
| 173 | |
| 174 | /* Definitions for DRTM address map */ |
| 175 | #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT U(55) |
| 176 | #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK ULL(0x3) |
| 177 | #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_NC ULL(0) |
| 178 | #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WC ULL(1) |
| 179 | #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WT ULL(2) |
| 180 | #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WB ULL(3) |
| 181 | |
| 182 | #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT U(52) |
| 183 | #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK ULL(0x7) |
| 184 | #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NORMAL ULL(0) |
| 185 | #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NCAR ULL(1) |
| 186 | #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_DEVICE ULL(2) |
| 187 | #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NV ULL(3) |
| 188 | #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_RSVD ULL(4) |
| 189 | |
| 190 | #define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT U(0) |
| 191 | #define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK ULL(0xFFFFFFFFFFFFF) |
| 192 | |
| 193 | #define ARM_DRTM_REGION_SIZE_TYPE_SET_CACHEABILITY(reg, val) \ |
| 194 | do { \ |
| 195 | reg = (((reg) & \ |
| 196 | ~(ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK << \ |
| 197 | ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT)) | \ |
| 198 | (((val) & \ |
| 199 | ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK) << \ |
| 200 | ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT)); \ |
| 201 | } while (false) |
| 202 | |
| 203 | #define ARM_DRTM_REGION_SIZE_TYPE_SET_REGION_TYPE(reg, val) \ |
| 204 | do { \ |
| 205 | reg = (((reg) & \ |
| 206 | ~(ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK << \ |
| 207 | ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT)) | \ |
| 208 | (((val) & ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK) \ |
| 209 | << ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT)); \ |
| 210 | } while (false) |
| 211 | |
| 212 | #define ARM_DRTM_REGION_SIZE_TYPE_SET_4K_PAGE_NUM(reg, val) \ |
| 213 | do { \ |
| 214 | reg = (((reg) & \ |
| 215 | ~(ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK << \ |
| 216 | ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT)) | \ |
| 217 | (((val) & ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK) \ |
| 218 | << ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT)); \ |
| 219 | } while (false) |
| 220 | |
Manish V Badarkhe | 8a76603 | 2022-02-23 11:26:53 +0000 | [diff] [blame] | 221 | /* Initialization routine for the DRTM service */ |
| 222 | int drtm_setup(void); |
| 223 | |
| 224 | /* Handler to be called to handle DRTM SMC calls */ |
| 225 | uint64_t drtm_smc_handler(uint32_t smc_fid, |
| 226 | uint64_t x1, |
| 227 | uint64_t x2, |
| 228 | uint64_t x3, |
| 229 | uint64_t x4, |
| 230 | void *cookie, |
| 231 | void *handle, |
| 232 | uint64_t flags); |
| 233 | |
| 234 | #endif /* ARM_DRTM_SVC_H */ |