blob: 22492c3d54842297b54b80b7ee22e5a20c8de973 [file] [log] [blame]
Govindraj Raja7beabfd2023-06-27 10:07:23 -05001/*
2 * Copyright (c) 2023, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef NEOVERSE_HERMES_H
8#define NEOVERSE_HERMES_H
9
10#define NEOVERSE_HERMES_MIDR U(0x410FD8E0)
11
12/*******************************************************************************
13 * CPU Extended Control register specific definitions
14 ******************************************************************************/
15#define NEOVERSE_HERMES_CPUECTLR_EL1 S3_0_C15_C1_4
16
17/*******************************************************************************
18 * CPU Power Control register specific definitions
19 ******************************************************************************/
20#define NEOVERSE_HERMES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
21#define NEOVERSE_HERMES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
22
23#endif /* NEOVERSE_HERMES_H */