blob: 51e3e53320688859e13d3abf0d075d32c18bf880 [file] [log] [blame]
Nariman Poushinc703f902018-03-07 10:29:57 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <bl_common.h>
8#include <debug.h>
9#include <plat_arm.h>
10#include <sgm_plat_config.h>
11#include <soc_css.h>
12
13void bl1_early_platform_setup(void)
14{
15 /* Initialize the platform configuration structure */
16 plat_config_init();
17
18 arm_bl1_early_platform_setup();
19
20#if !HW_ASSISTED_COHERENCY
21 /*
22 * Initialize Interconnect for this cluster during cold boot.
23 * No need for locks as no other CPU is active.
24 */
25 plat_arm_interconnect_init();
26 /*
27 * Enable Interconnect coherency for the primary CPU's cluster.
28 */
29 plat_arm_interconnect_enter_coherency();
30#endif
31}