blob: 13f413b556432c6379f991b87da3450ccfb790db [file] [log] [blame]
Biju Das54f6a432020-12-07 16:31:01 +00001/*
2 * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <string.h>
8
9#include <arch_helpers.h>
10#include <bl1/bl1.h>
11#include <common/bl_common.h>
12#include <common/debug.h>
13#include <common/desc_image_load.h>
14#include <drivers/console.h>
15#include <drivers/io/io_driver.h>
16#include <drivers/io/io_storage.h>
17#include <libfdt.h>
18#include <lib/mmio.h>
19#include <lib/xlat_tables/xlat_tables_defs.h>
20#include <platform_def.h>
21#include <plat/common/platform.h>
22
23#include "avs_driver.h"
24#include "board.h"
25#include "boot_init_dram.h"
26#include "cpg_registers.h"
27#include "emmc_def.h"
28#include "emmc_hal.h"
29#include "emmc_std.h"
30#include "io_common.h"
31#include "io_rcar.h"
32#include "qos_init.h"
33#include "rcar_def.h"
34#include "rcar_private.h"
35#include "rcar_version.h"
36#include "rom_api.h"
37
38#define MAX_DRAM_CHANNELS 4
Biju Dase8781e72020-12-18 17:41:01 +000039/*
40 * DDR ch0 has a shadow area mapped in 32bit address space.
41 * Physical address 0x4_0000_0000 - 0x4_7fff_ffff in 64bit space
42 * is mapped to 0x4000_0000 - 0xbfff_ffff in 32bit space.
43 */
44#define MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE 0x80000000ULL
Biju Das54f6a432020-12-07 16:31:01 +000045
46#if RCAR_BL2_DCACHE == 1
47/*
48 * Following symbols are only used during plat_arch_setup() only
49 * when RCAR_BL2_DCACHE is enabled.
50 */
51static const uint64_t BL2_RO_BASE = BL_CODE_BASE;
52static const uint64_t BL2_RO_LIMIT = BL_CODE_END;
53
54#if USE_COHERENT_MEM
55static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
56static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
57#endif /* USE_COHERENT_MEM */
58
59#endif /* RCAR_BL2_DCACHE */
60
61extern void plat_rcar_gic_driver_init(void);
62extern void plat_rcar_gic_init(void);
63extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info);
64extern void bl2_system_cpg_init(void);
65extern void bl2_secure_setting(void);
66extern void bl2_cpg_init(void);
67extern void rcar_io_emmc_setup(void);
68extern void rcar_io_setup(void);
69extern void rcar_swdt_release(void);
70extern void rcar_swdt_init(void);
71extern void rcar_rpc_init(void);
72extern void rcar_dma_init(void);
73extern void rzg_pfc_init(void);
74
75static void bl2_init_generic_timer(void);
76
77/* RZ/G2 product check */
78#if RCAR_LSI == RZ_G2M
79#define TARGET_PRODUCT PRR_PRODUCT_M3
80#define TARGET_NAME "RZ/G2M"
81#elif RCAR_LSI == RCAR_AUTO
82#define TARGET_NAME "RZ/G2M"
83#endif /* RCAR_LSI == RZ_G2M */
84
85#define GPIO_INDT (GPIO_INDT1)
86#define GPIO_BKUP_TRG_SHIFT (1U << 8U)
87
88CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100)
89 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE),
90 assert_bl31_params_do_not_fit_in_shared_memory);
91
92static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
93
94/* FDT with DRAM configuration */
95uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)];
96static void *fdt = (void *)fdt_blob;
97
98static void unsigned_num_print(uint64_t unum, unsigned int radix, char *string)
99{
100 /* Just need enough space to store 64 bit decimal integer */
101 char num_buf[20];
102 int i = 0;
103 unsigned int rem;
104
105 do {
106 rem = unum % radix;
107 if (rem < 0xaU) {
108 num_buf[i] = '0' + rem;
109 } else {
110 num_buf[i] = 'a' + (rem - 0xaU);
111 }
112 i++;
113 unum /= radix;
114 } while (unum > 0U);
115
116 while (--i >= 0) {
117 *string++ = num_buf[i];
118 }
119 *string = 0;
120}
121
122#if RCAR_LOSSY_ENABLE == 1
123typedef struct bl2_lossy_info {
124 uint32_t magic;
125 uint32_t a0;
126 uint32_t b0;
127} bl2_lossy_info_t;
128
129static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr,
130 uint64_t end_addr, uint32_t format,
131 uint32_t enable, int fcnlnode)
132{
133 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr);
134 char nodename[40] = { 0 };
135 int ret, node;
136
137 /* Ignore undefined addresses */
138 if (start_addr == 0UL && end_addr == 0UL) {
139 return;
140 }
141
142 snprintf(nodename, sizeof(nodename), "lossy-decompression@");
143 unsigned_num_print(start_addr, 16, nodename + strlen(nodename));
144
145 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename);
146 if (ret < 0) {
147 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret);
148 panic();
149 }
150
151 ret = fdt_setprop_string(fdt, node, "compatible",
152 "renesas,lossy-decompression");
153 if (ret < 0) {
154 NOTICE("BL2: Cannot add FCNL compat string %s (ret=%i)\n",
155 "renesas,lossy-decompression", ret);
156 panic();
157 }
158
159 ret = fdt_appendprop_string(fdt, node, "compatible",
160 "shared-dma-pool");
161 if (ret < 0) {
162 NOTICE("BL2: Cannot append FCNL compat string %s (ret=%i)\n",
163 "shared-dma-pool", ret);
164 panic();
165 }
166
167 ret = fdt_setprop_u64(fdt, node, "reg", start_addr);
168 if (ret < 0) {
169 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret);
170 panic();
171 }
172
173 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize));
174 if (ret < 0) {
175 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret);
176 panic();
177 }
178
179 ret = fdt_setprop(fdt, node, "no-map", NULL, 0);
180 if (ret < 0) {
181 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret);
182 panic();
183 }
184
185 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format);
186 if (ret < 0) {
187 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret);
188 panic();
189 }
190}
191
192static void bl2_lossy_setting(uint32_t no, uint64_t start_addr,
193 uint64_t end_addr, uint32_t format,
194 uint32_t enable, int fcnlnode)
195{
196 bl2_lossy_info_t info;
197 uint32_t reg;
198
199 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode);
200
201 reg = format | (start_addr >> 20);
202 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg);
203 mmio_write_32(AXI_DCMPAREACRB0 + 0x8U * no, end_addr >> 20);
204 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg | enable);
205
206 info.magic = 0x12345678U;
207 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no);
208 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8U * no);
209
210 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic);
211 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4U, info.a0);
212 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8U, info.b0);
213
214 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no,
215 mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no),
216 mmio_read_32(AXI_DCMPAREACRB0 + 0x8U * no));
217}
218#endif /* RCAR_LOSSY_ENABLE == 1 */
219
220void bl2_plat_flush_bl31_params(void)
221{
222 uint32_t product_cut, product, cut;
223 uint32_t boot_dev, boot_cpu;
224 uint32_t reg;
225
226 reg = mmio_read_32(RCAR_MODEMR);
227 boot_dev = reg & MODEMR_BOOT_DEV_MASK;
228
229 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
230 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) {
231 emmc_terminate();
232 }
233
234 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) {
235 bl2_secure_setting();
236 }
237
238 reg = mmio_read_32(RCAR_PRR);
239 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
240 product = reg & PRR_PRODUCT_MASK;
241 cut = reg & PRR_CUT_MASK;
242
243 if (!((product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) ||
244 (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20))) {
245 /* Disable MFIS write protection */
246 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1U);
247 }
248
249 reg = mmio_read_32(RCAR_MODEMR);
250 boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
251 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
252 boot_cpu == MODEMR_BOOT_CPU_CA53) {
253 if (product_cut == PRR_PRODUCT_H3_CUT20) {
254 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
255 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE);
256 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
257 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE);
258 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE);
259 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE);
260 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
261 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) {
262 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
263 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
264 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) ||
265 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) {
266 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
267 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE);
268 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
269 }
270
271 if (product_cut == (PRR_PRODUCT_H3_CUT20) ||
272 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
273 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) ||
274 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) {
275 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE);
276 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE);
277 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE);
278
279 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE);
280 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE);
281 }
282 }
283
284 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE);
285 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT);
286
287 rcar_swdt_release();
288 bl2_system_cpg_init();
289
290#if RCAR_BL2_DCACHE == 1
291 /* Disable data cache (clean and invalidate) */
292 disable_mmu_el3();
293#endif /* RCAR_BL2_DCACHE == 1 */
294}
295
296static uint32_t is_ddr_backup_mode(void)
297{
298#if RCAR_SYSTEM_SUSPEND
299 static uint32_t reason = RCAR_COLD_BOOT;
300 static uint32_t once;
301
302 if (once != 0U) {
303 return reason;
304 }
305
306 once = 1;
307 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0U) {
308 return reason;
309 }
310
311 reason = RCAR_WARM_BOOT;
312 return reason;
313#else /* RCAR_SYSTEM_SUSPEND */
314 return RCAR_COLD_BOOT;
315#endif /* RCAR_SYSTEM_SUSPEND */
316}
317
318int bl2_plat_handle_pre_image_load(unsigned int image_id)
319{
320 u_register_t *boot_kind = (void *)BOOT_KIND_BASE;
321 bl_mem_params_node_t *bl_mem_params;
322
323 if (image_id != BL31_IMAGE_ID) {
324 return 0;
325 }
326
327 bl_mem_params = get_bl_mem_params_node(image_id);
328
329 if (is_ddr_backup_mode() != RCAR_COLD_BOOT) {
330 *boot_kind = RCAR_WARM_BOOT;
331 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
332
333 console_flush();
334 bl2_plat_flush_bl31_params();
335
336 /* will not return */
337 bl2_enter_bl31(&bl_mem_params->ep_info);
338 }
339
340 *boot_kind = RCAR_COLD_BOOT;
341 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
342
343 return 0;
344}
345
346static uint64_t rzg_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest)
347{
348 uint32_t cert, len;
349 int err;
350
351 err = rcar_get_certificate(certid, &cert);
352 if (err != 0) {
353 ERROR("%s : cert file load error", __func__);
354 return 1U;
355 }
356
357 rcar_read_certificate((uint64_t)cert, &len, dest);
358
359 return 0U;
360}
361
362int bl2_plat_handle_post_image_load(unsigned int image_id)
363{
364 static bl2_to_bl31_params_mem_t *params;
365 bl_mem_params_node_t *bl_mem_params;
366 uintptr_t dest;
367 uint64_t ret;
368
369 if (params == NULL) {
370 params = (bl2_to_bl31_params_mem_t *)PARAMS_BASE;
371 memset((void *)PARAMS_BASE, 0, sizeof(*params));
372 }
373
374 bl_mem_params = get_bl_mem_params_node(image_id);
375
376 switch (image_id) {
377 case BL31_IMAGE_ID:
378 ret = rzg_get_dest_addr_from_cert(SOC_FW_CONTENT_CERT_ID,
379 &dest);
380 if (ret == 0U) {
381 bl_mem_params->image_info.image_base = dest;
382 }
383 break;
384 case BL32_IMAGE_ID:
385 ret = rzg_get_dest_addr_from_cert(TRUSTED_OS_FW_CONTENT_CERT_ID,
386 &dest);
387 if (ret == 0U) {
388 bl_mem_params->image_info.image_base = dest;
389 }
390
391 memcpy(&params->bl32_ep_info, &bl_mem_params->ep_info,
392 sizeof(entry_point_info_t));
393 break;
394 case BL33_IMAGE_ID:
395 memcpy(&params->bl33_ep_info, &bl_mem_params->ep_info,
396 sizeof(entry_point_info_t));
397 break;
398 default:
399 break;
400 }
401
402 return 0;
403}
404
405struct meminfo *bl2_plat_sec_mem_layout(void)
406{
407 return &bl2_tzram_layout;
408}
409
410static void bl2_populate_compatible_string(void *dt)
411{
412 uint32_t board_type;
413 uint32_t board_rev;
414 uint32_t reg;
415 int ret;
416
417 fdt_setprop_u32(dt, 0, "#address-cells", 2);
418 fdt_setprop_u32(dt, 0, "#size-cells", 2);
419
420 /* Populate compatible string */
421 rzg_get_board_type(&board_type, &board_rev);
422 switch (board_type) {
423 case BOARD_HIHOPE_RZ_G2M:
424 ret = fdt_setprop_string(dt, 0, "compatible",
425 "hoperun,hihope-rzg2m");
426 break;
427 default:
428 NOTICE("BL2: Cannot set compatible string, board unsupported\n");
429 panic();
430 break;
431 }
432
433 if (ret < 0) {
434 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret);
435 panic();
436 }
437
438 reg = mmio_read_32(RCAR_PRR);
439 switch (reg & PRR_PRODUCT_MASK) {
440 case PRR_PRODUCT_M3:
441 ret = fdt_appendprop_string(dt, 0, "compatible",
442 "renesas,r8a774a1");
443 break;
444 default:
445 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n");
446 panic();
447 break;
448 }
449
450 if (ret < 0) {
451 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret);
452 panic();
453 }
454}
455
Biju Dase8781e72020-12-18 17:41:01 +0000456static int bl2_add_memory_node(uint64_t start, uint64_t size)
Biju Das54f6a432020-12-07 16:31:01 +0000457{
458 char nodename[32] = { 0 };
Biju Das54f6a432020-12-07 16:31:01 +0000459 uint64_t fdtsize;
Biju Dase8781e72020-12-18 17:41:01 +0000460 int ret, node;
461
462 fdtsize = cpu_to_fdt64(size);
463
464 snprintf(nodename, sizeof(nodename), "memory@");
465 unsigned_num_print(start, 16, nodename + strlen(nodename));
466 node = ret = fdt_add_subnode(fdt, 0, nodename);
467 if (ret < 0) {
468 return ret;
469 }
470
471 ret = fdt_setprop_string(fdt, node, "device_type", "memory");
472 if (ret < 0) {
473 return ret;
474 }
475
476 ret = fdt_setprop_u64(fdt, node, "reg", start);
477 if (ret < 0) {
478 return ret;
479 }
480
481 return fdt_appendprop(fdt, node, "reg", &fdtsize, sizeof(fdtsize));
482}
483
484static void bl2_advertise_dram_entries(uint64_t dram_config[8])
485{
486 uint64_t start, size;
487 int ret, chan;
Biju Das54f6a432020-12-07 16:31:01 +0000488
489 for (chan = 0; chan < MAX_DRAM_CHANNELS; chan++) {
490 start = dram_config[2 * chan];
491 size = dram_config[2 * chan + 1];
492 if (size == 0U) {
493 continue;
494 }
495
496 NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n",
497 chan, start, start + size - 1U,
498 (size >> 30) ? : size >> 20,
499 (size >> 30) ? "G" : "M");
500 }
501
502 /*
503 * We add the DT nodes in reverse order here. The fdt_add_subnode()
504 * adds the DT node before the first existing DT node, so we have
505 * to add them in reverse order to get nodes sorted by address in
506 * the resulting DT.
507 */
508 for (chan = MAX_DRAM_CHANNELS - 1; chan >= 0; chan--) {
509 start = dram_config[2 * chan];
510 size = dram_config[2 * chan + 1];
511 if (size == 0U) {
512 continue;
513 }
514
515 /*
516 * Channel 0 is mapped in 32bit space and the first
517 * 128 MiB are reserved
518 */
519 if (chan == 0) {
Biju Dase8781e72020-12-18 17:41:01 +0000520 /*
521 * Maximum DDR size in Channel 0 for 32 bit space is 2GB, Add DT node
522 * for remaining region in 64 bit address space
523 */
524 if (size > MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE) {
525 start = dram_config[chan] + MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE;
526 size -= MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE;
527 ret = bl2_add_memory_node(start, size);
528 if (ret < 0) {
529 goto err;
530 }
531 }
Biju Das54f6a432020-12-07 16:31:01 +0000532 start = 0x48000000U;
533 size -= 0x8000000U;
534 }
535
Biju Dase8781e72020-12-18 17:41:01 +0000536 ret = bl2_add_memory_node(start, size);
Biju Das54f6a432020-12-07 16:31:01 +0000537 if (ret < 0) {
538 goto err;
539 }
540 }
541
542 return;
543err:
544 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret);
545 panic();
546}
547
548static void bl2_advertise_dram_size(uint32_t product)
549{
550 uint64_t dram_config[8] = {
551 [0] = 0x400000000ULL,
552 [2] = 0x500000000ULL,
553 [4] = 0x600000000ULL,
554 [6] = 0x700000000ULL,
555 };
556
557 switch (product) {
558 case PRR_PRODUCT_M3:
559 /* 4GB(2GBx2 2ch split) */
560 dram_config[1] = 0x80000000ULL;
561 dram_config[5] = 0x80000000ULL;
562 break;
563 default:
564 NOTICE("BL2: Detected invalid DRAM entries\n");
565 break;
566 }
567
568 bl2_advertise_dram_entries(dram_config);
569}
570
571void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
572 u_register_t arg3, u_register_t arg4)
573{
574 uint32_t reg, midr, boot_dev, boot_cpu, type, rev;
575 uint32_t product, product_cut, major, minor;
576 int32_t ret;
577 const char *str;
578 const char *unknown = "unknown";
579 const char *cpu_ca57 = "CA57";
580 const char *cpu_ca53 = "CA53";
581 const char *product_g2m = "G2M";
582 const char *boot_hyper80 = "HyperFlash(80MHz)";
583 const char *boot_qspi40 = "QSPI Flash(40MHz)";
584 const char *boot_qspi80 = "QSPI Flash(80MHz)";
585 const char *boot_emmc25x1 = "eMMC(25MHz x1)";
586 const char *boot_emmc50x8 = "eMMC(50MHz x8)";
587 const char *boot_hyper160 = "HyperFlash(160MHz)";
588#if RZG_LCS_STATE_DETECTION_ENABLE
589 uint32_t lcs;
590 const char *lcs_secure = "SE";
591 const char *lcs_cm = "CM";
592 const char *lcs_dm = "DM";
593 const char *lcs_sd = "SD";
594 const char *lcs_fa = "FA";
595#endif /* RZG_LCS_STATE_DETECTION_ENABLE */
596
597#if (RCAR_LOSSY_ENABLE == 1)
598 int fcnlnode;
599#endif /* (RCAR_LOSSY_ENABLE == 1) */
600
601 bl2_init_generic_timer();
602
603 reg = mmio_read_32(RCAR_MODEMR);
604 boot_dev = reg & MODEMR_BOOT_DEV_MASK;
605 boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
606
607 bl2_cpg_init();
608
609 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
610 boot_cpu == MODEMR_BOOT_CPU_CA53) {
611 rzg_pfc_init();
612 rcar_console_boot_init();
613 }
614
615 plat_rcar_gic_driver_init();
616 plat_rcar_gic_init();
617 rcar_swdt_init();
618
619 /* FIQ interrupts are taken to EL3 */
620 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
621
622 write_daifclr(DAIF_FIQ_BIT);
623
624 reg = read_midr();
625 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT);
626 switch (midr) {
627 case MIDR_CA57:
628 str = cpu_ca57;
629 break;
630 case MIDR_CA53:
631 str = cpu_ca53;
632 break;
633 default:
634 str = unknown;
635 break;
636 }
637
638 NOTICE("BL2: RZ/G2 Initial Program Loader(%s) Rev.%s\n", str,
639 version_of_renesas);
640
641 reg = mmio_read_32(RCAR_PRR);
642 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
643 product = reg & PRR_PRODUCT_MASK;
644
645 switch (product) {
646 case PRR_PRODUCT_M3:
647 str = product_g2m;
648 break;
649 default:
650 str = unknown;
651 break;
652 }
653
654 if ((product == PRR_PRODUCT_M3) &&
655 ((reg & RCAR_MAJOR_MASK) == PRR_PRODUCT_20)) {
656 if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) {
657 /* M3 Ver.1.1 or Ver.1.2 */
658 NOTICE("BL2: PRR is RZ/%s Ver.1.1 / Ver.1.2\n", str);
659 } else {
660 NOTICE("BL2: PRR is RZ/%s Ver.1.%d\n", str,
661 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET);
662 }
663 } else {
664 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT;
665 major = major + RCAR_MAJOR_OFFSET;
666 minor = reg & RCAR_MINOR_MASK;
667 NOTICE("BL2: PRR is RZ/%s Ver.%d.%d\n", str, major, minor);
668 }
669
670 rzg_get_board_type(&type, &rev);
671
672 switch (type) {
673 case BOARD_HIHOPE_RZ_G2M:
674 break;
675 default:
676 type = BOARD_UNKNOWN;
677 break;
678 }
679
680 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) {
681 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type));
682 } else {
683 NOTICE("BL2: Board is %s Rev.%d.%d\n",
684 GET_BOARD_NAME(type),
685 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev));
686 }
687
688#if RCAR_LSI != RCAR_AUTO
689 if (product != TARGET_PRODUCT) {
690 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME);
691 ERROR("BL2: Please write the correct IPL to flash memory.\n");
692 panic();
693 }
694#endif /* RCAR_LSI != RCAR_AUTO */
695 rcar_avs_init();
696 rcar_avs_setting();
697
698 switch (boot_dev) {
699 case MODEMR_BOOT_DEV_HYPERFLASH160:
700 str = boot_hyper160;
701 break;
702 case MODEMR_BOOT_DEV_HYPERFLASH80:
703 str = boot_hyper80;
704 break;
705 case MODEMR_BOOT_DEV_QSPI_FLASH40:
706 str = boot_qspi40;
707 break;
708 case MODEMR_BOOT_DEV_QSPI_FLASH80:
709 str = boot_qspi80;
710 break;
711 case MODEMR_BOOT_DEV_EMMC_25X1:
712 str = boot_emmc25x1;
713 break;
714 case MODEMR_BOOT_DEV_EMMC_50X8:
715 str = boot_emmc50x8;
716 break;
717 default:
718 str = unknown;
719 break;
720 }
721 NOTICE("BL2: Boot device is %s\n", str);
722
723 rcar_avs_setting();
724
725#if RZG_LCS_STATE_DETECTION_ENABLE
726 reg = rcar_rom_get_lcs(&lcs);
727 if (reg != 0U) {
728 str = unknown;
729 goto lcm_state;
730 }
731
732 switch (lcs) {
733 case LCS_CM:
734 str = lcs_cm;
735 break;
736 case LCS_DM:
737 str = lcs_dm;
738 break;
739 case LCS_SD:
740 str = lcs_sd;
741 break;
742 case LCS_SE:
743 str = lcs_secure;
744 break;
745 case LCS_FA:
746 str = lcs_fa;
747 break;
748 default:
749 str = unknown;
750 break;
751 }
752
753lcm_state:
754 NOTICE("BL2: LCM state is %s\n", str);
755#endif /* RZG_LCS_STATE_DETECTION_ENABLE */
756
757 rcar_avs_end();
758 is_ddr_backup_mode();
759
760 bl2_tzram_layout.total_base = BL31_BASE;
761 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE;
762
763 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
764 boot_cpu == MODEMR_BOOT_CPU_CA53) {
765 ret = rzg_dram_init();
766 if (ret != 0) {
767 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret);
768 panic();
769 }
770 rzg_qos_init();
771 }
772
773 /* Set up FDT */
774 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob));
775 if (ret != 0) {
776 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret);
777 panic();
778 }
779
780 /* Add platform compatible string */
781 bl2_populate_compatible_string(fdt);
782
783 /* Print DRAM layout */
784 bl2_advertise_dram_size(product);
785
786 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
787 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) {
788 if (rcar_emmc_init() != EMMC_SUCCESS) {
789 NOTICE("BL2: Failed to eMMC driver initialize.\n");
790 panic();
791 }
792 rcar_emmc_memcard_power(EMMC_POWER_ON);
793 if (rcar_emmc_mount() != EMMC_SUCCESS) {
794 NOTICE("BL2: Failed to eMMC mount operation.\n");
795 panic();
796 }
797 } else {
798 rcar_rpc_init();
799 rcar_dma_init();
800 }
801
802 reg = mmio_read_32(RST_WDTRSTCR);
803 reg &= ~WDTRSTCR_RWDT_RSTMSK;
804 reg |= WDTRSTCR_PASSWORD;
805 mmio_write_32(RST_WDTRSTCR, reg);
806
807 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD);
808 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD);
809
810 reg = mmio_read_32(RCAR_PRR);
811 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) {
812 mmio_write_32(CPG_CA57DBGRCR,
813 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR));
814 }
815
816 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) {
817 mmio_write_32(CPG_CA53DBGRCR,
818 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR));
819 }
820
821 if (product_cut == PRR_PRODUCT_H3_CUT10) {
822 reg = mmio_read_32(CPG_PLL2CR);
823 reg &= ~((uint32_t)1 << 5);
824 mmio_write_32(CPG_PLL2CR, reg);
825
826 reg = mmio_read_32(CPG_PLL4CR);
827 reg &= ~((uint32_t)1 << 5);
828 mmio_write_32(CPG_PLL4CR, reg);
829
830 reg = mmio_read_32(CPG_PLL0CR);
831 reg &= ~((uint32_t)1 << 12);
832 mmio_write_32(CPG_PLL0CR, reg);
833 }
834#if (RCAR_LOSSY_ENABLE == 1)
835 NOTICE("BL2: Lossy Decomp areas\n");
836
837 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory");
838 if (fcnlnode < 0) {
839 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n",
840 fcnlnode);
841 panic();
842 }
843
844 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0,
845 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode);
846 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1,
847 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode);
848 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2,
849 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode);
850#endif /* RCAR_LOSSY_ENABLE */
851
852 fdt_pack(fdt);
853 NOTICE("BL2: FDT at %p\n", fdt);
854
855 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
856 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) {
857 rcar_io_emmc_setup();
858 } else {
859 rcar_io_setup();
860 }
861}
862
863void bl2_el3_plat_arch_setup(void)
864{
865#if RCAR_BL2_DCACHE == 1
866 NOTICE("BL2: D-Cache enable\n");
867 rcar_configure_mmu_el3(BL2_BASE,
868 BL2_END - BL2_BASE,
869 BL2_RO_BASE, BL2_RO_LIMIT
870#if USE_COHERENT_MEM
871 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT
872#endif /* USE_COHERENT_MEM */
873 );
874#endif /* RCAR_BL2_DCACHE == 1 */
875}
876
877void bl2_platform_setup(void)
878{
879 /*
880 * Place holder for performing any platform initialization specific
881 * to BL2.
882 */
883}
884
885static void bl2_init_generic_timer(void)
886{
887 uint32_t reg_cntfid;
888 uint32_t modemr;
889 uint32_t modemr_pll;
890 uint32_t pll_table[] = {
891 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */
892 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */
893 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */
894 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */
895 };
896
897 modemr = mmio_read_32(RCAR_MODEMR);
898 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK);
899
900 /* Set frequency data in CNTFID0 */
901 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
902
903 /* Update memory mapped and register based frequency */
904 write_cntfrq_el0((u_register_t)reg_cntfid);
905 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid);
906 /* Enable counter */
907 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF,
908 (uint32_t)CNTCR_EN);
909}