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Konstantin Porotchkin62a76462018-02-26 15:51:11 +02001/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8/* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */
9
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000010#ifndef CCU_H
11#define CCU_H
Konstantin Porotchkin62a76462018-02-26 15:51:11 +020012
13#ifndef __ASSEMBLY__
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <drivers/marvell/addr_map.h>
Konstantin Porotchkin62a76462018-02-26 15:51:11 +020015#endif
16
17/* CCU registers definitions */
18#define CCU_WIN_CR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x0 + \
19 (0x10 * win))
20#define CCU_TARGET_ID_OFFSET (8)
21#define CCU_TARGET_ID_MASK (0x7F)
22
23#define CCU_WIN_SCR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x4 + \
24 (0x10 * win))
25#define CCU_WIN_ENA_WRITE_SECURE (0x1)
26#define CCU_WIN_ENA_READ_SECURE (0x2)
27
28#define CCU_WIN_ALR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x8 + \
29 (0x10 * win))
30#define CCU_WIN_AHR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0xC + \
31 (0x10 * win))
32
33#define CCU_WIN_GCR_OFFSET(ap) (MVEBU_CCU_BASE(ap) + 0xD0)
34#define CCU_GCR_TARGET_OFFSET (8)
35#define CCU_GCR_TARGET_MASK (0xFF)
36
37#define CCU_SRAM_WIN_CR CCU_WIN_CR_OFFSET(MVEBU_AP0, 1)
38
39#ifndef __ASSEMBLY__
40int init_ccu(int);
41void ccu_win_check(struct addr_map_win *win);
42void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id);
43void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
44void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
45void ccu_dram_win_config(int ap_index, struct addr_map_win *win);
46void ccu_dram_target_set(int ap_index, uint32_t target);
47void ccu_save_win_all(int ap_id);
48void ccu_restore_win_all(int ap_id);
49#endif
50
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000051#endif /* CCU_H */