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Haojian Zhuang934ae712017-05-24 08:47:49 +08001/*
Haojian Zhuang3bd94382018-01-28 23:33:02 +08002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Haojian Zhuang934ae712017-05-24 08:47:49 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
8#include <assert.h>
9#include <bl_common.h>
Haojian Zhuang934ae712017-05-24 08:47:49 +080010#include <debug.h>
Haojian Zhuangf4de6532018-10-31 17:41:35 +080011#include <delay_timer.h>
Victor Chong2d9a42d2017-08-17 15:21:10 +090012#include <desc_image_load.h>
Haojian Zhuang934ae712017-05-24 08:47:49 +080013#include <dw_mmc.h>
Haojian Zhuang934ae712017-05-24 08:47:49 +080014#include <errno.h>
15#include <hi6220.h>
16#include <hisi_mcu.h>
17#include <hisi_sram_map.h>
Haojian Zhuange9713772018-08-04 18:07:10 +080018#include <mmc.h>
Haojian Zhuang934ae712017-05-24 08:47:49 +080019#include <mmio.h>
Victor Chong7d787f52017-08-16 13:53:56 +090020#ifdef SPD_opteed
21#include <optee_utils.h>
22#endif
Jerome Forissieraebe95d2018-11-08 10:17:47 +000023#include <pl011.h>
Haojian Zhuangb755da32018-01-25 16:10:14 +080024#include <platform.h>
Michael Brandlafdff3c2018-02-22 16:30:30 +010025#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/
Haojian Zhuang934ae712017-05-24 08:47:49 +080026#include <string.h>
27
Haojian Zhuang934ae712017-05-24 08:47:49 +080028#include "hikey_private.h"
29
30/*
31 * The next 2 constants identify the extents of the code & RO data region.
32 * These addresses are used by the MMU setup code and therefore they must be
33 * page-aligned. It is the responsibility of the linker script to ensure that
34 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
35 */
36#define BL2_RO_BASE (unsigned long)(&__RO_START__)
37#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
38
Haojian Zhuangb755da32018-01-25 16:10:14 +080039#define BL2_RW_BASE (BL2_RO_LIMIT)
40
Haojian Zhuang934ae712017-05-24 08:47:49 +080041/*
42 * The next 2 constants identify the extents of the coherent memory region.
43 * These addresses are used by the MMU setup code and therefore they must be
44 * page-aligned. It is the responsibility of the linker script to ensure that
45 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
46 * page-aligned addresses.
47 */
48#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
49#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
50
Haojian Zhuangb755da32018-01-25 16:10:14 +080051static meminfo_t bl2_el3_tzram_layout;
Jerome Forissieraebe95d2018-11-08 10:17:47 +000052static console_pl011_t console;
Haojian Zhuangb755da32018-01-25 16:10:14 +080053
54enum {
55 BOOT_MODE_RECOVERY = 0,
56 BOOT_MODE_NORMAL,
57 BOOT_MODE_MASK = 1,
58};
Haojian Zhuang934ae712017-05-24 08:47:49 +080059
Victor Chong2d9a42d2017-08-17 15:21:10 +090060/*******************************************************************************
61 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
62 * Return 0 on success, -1 otherwise.
63 ******************************************************************************/
Victor Chong2d9a42d2017-08-17 15:21:10 +090064int plat_hikey_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
Haojian Zhuang934ae712017-05-24 08:47:49 +080065{
66 /* Enable MCU SRAM */
67 hisi_mcu_enable_sram();
68
69 /* Load MCU binary into SRAM */
70 hisi_mcu_load_image(scp_bl2_image_info->image_base,
71 scp_bl2_image_info->image_size);
72 /* Let MCU running */
73 hisi_mcu_start_run();
74
75 INFO("%s: MCU PC is at 0x%x\n",
76 __func__, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2));
77 INFO("%s: AO_SC_PERIPH_CLKSTAT4 is 0x%x\n",
78 __func__, mmio_read_32(AO_SC_PERIPH_CLKSTAT4));
79 return 0;
80}
81
Victor Chong2d9a42d2017-08-17 15:21:10 +090082/*******************************************************************************
83 * Gets SPSR for BL32 entry
84 ******************************************************************************/
85uint32_t hikey_get_spsr_for_bl32_entry(void)
86{
87 /*
88 * The Secure Payload Dispatcher service is responsible for
89 * setting the SPSR prior to entry into the BL3-2 image.
90 */
91 return 0;
92}
93
94/*******************************************************************************
95 * Gets SPSR for BL33 entry
96 ******************************************************************************/
97#ifndef AARCH32
98uint32_t hikey_get_spsr_for_bl33_entry(void)
99{
100 unsigned int mode;
101 uint32_t spsr;
102
103 /* Figure out what mode we enter the non-secure world in */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000104 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
Victor Chong2d9a42d2017-08-17 15:21:10 +0900105
106 /*
107 * TODO: Consider the possibility of specifying the SPSR in
108 * the FIP ToC and allowing the platform to have a say as
109 * well.
110 */
111 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
112 return spsr;
113}
114#else
115uint32_t hikey_get_spsr_for_bl33_entry(void)
116{
117 unsigned int hyp_status, mode, spsr;
118
119 hyp_status = GET_VIRT_EXT(read_id_pfr1());
120
121 mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
122
123 /*
124 * TODO: Consider the possibility of specifying the SPSR in
125 * the FIP ToC and allowing the platform to have a say as
126 * well.
127 */
128 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
129 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
130 return spsr;
131}
132#endif /* AARCH32 */
133
Victor Chong2d9a42d2017-08-17 15:21:10 +0900134int hikey_bl2_handle_post_image_load(unsigned int image_id)
135{
136 int err = 0;
137 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Victor Chong7d787f52017-08-16 13:53:56 +0900138#ifdef SPD_opteed
139 bl_mem_params_node_t *pager_mem_params = NULL;
140 bl_mem_params_node_t *paged_mem_params = NULL;
141#endif
Victor Chong2d9a42d2017-08-17 15:21:10 +0900142 assert(bl_mem_params);
143
144 switch (image_id) {
145#ifdef AARCH64
146 case BL32_IMAGE_ID:
Victor Chong7d787f52017-08-16 13:53:56 +0900147#ifdef SPD_opteed
148 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
149 assert(pager_mem_params);
150
151 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
152 assert(paged_mem_params);
153
154 err = parse_optee_header(&bl_mem_params->ep_info,
155 &pager_mem_params->image_info,
156 &paged_mem_params->image_info);
157 if (err != 0) {
158 WARN("OPTEE header parse error.\n");
159 }
160#endif
Victor Chong2d9a42d2017-08-17 15:21:10 +0900161 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl32_entry();
162 break;
163#endif
164
165 case BL33_IMAGE_ID:
166 /* BL33 expects to receive the primary CPU MPID (through r0) */
167 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
168 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl33_entry();
169 break;
170
171#ifdef SCP_BL2_BASE
172 case SCP_BL2_IMAGE_ID:
173 /* The subsequent handling of SCP_BL2 is platform specific */
174 err = plat_hikey_bl2_handle_scp_bl2(&bl_mem_params->image_info);
175 if (err) {
176 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
177 }
178 break;
179#endif
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000180 default:
181 /* Do nothing in default case */
182 break;
Victor Chong2d9a42d2017-08-17 15:21:10 +0900183 }
184
185 return err;
186}
187
188/*******************************************************************************
189 * This function can be used by the platforms to update/use image
190 * information for given `image_id`.
191 ******************************************************************************/
192int bl2_plat_handle_post_image_load(unsigned int image_id)
193{
194 return hikey_bl2_handle_post_image_load(image_id);
195}
Haojian Zhuang934ae712017-05-24 08:47:49 +0800196
197static void reset_dwmmc_clk(void)
198{
199 unsigned int data;
200
201 /* disable mmc0 bus clock */
202 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0);
203 do {
204 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
205 } while (data & PERI_CLK0_MMC0);
206 /* enable mmc0 bus clock */
207 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0);
208 do {
209 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
210 } while (!(data & PERI_CLK0_MMC0));
211 /* reset mmc0 clock domain */
212 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0);
213
214 /* bypass mmc0 clock phase */
215 data = mmio_read_32(PERI_SC_PERIPH_CTRL2);
216 data |= 3;
217 mmio_write_32(PERI_SC_PERIPH_CTRL2, data);
218
219 /* disable low power */
220 data = mmio_read_32(PERI_SC_PERIPH_CTRL13);
221 data |= 1 << 3;
222 mmio_write_32(PERI_SC_PERIPH_CTRL13, data);
223 do {
224 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
225 } while (!(data & PERI_RST0_MMC0));
226
227 /* unreset mmc0 clock domain */
228 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0);
229 do {
230 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
231 } while (data & PERI_RST0_MMC0);
232}
233
234static void hikey_boardid_init(void)
235{
236 u_register_t midr;
237
238 midr = read_midr();
239 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr);
240 INFO("[BDID] [%x] midr: 0x%x\n", MEMORY_AXI_CHIP_ADDR,
241 (unsigned int)midr);
242
243 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0);
244 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b);
245
246 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234);
247 mmio_write_32(ACPU_ARM64_FLAGB, 0x5678);
248}
249
250static void hikey_sd_init(void)
251{
252 /* switch pinmux to SD */
253 mmio_write_32(IOMG_SD_CLK, IOMG_MUX_FUNC0);
254 mmio_write_32(IOMG_SD_CMD, IOMG_MUX_FUNC0);
255 mmio_write_32(IOMG_SD_DATA0, IOMG_MUX_FUNC0);
256 mmio_write_32(IOMG_SD_DATA1, IOMG_MUX_FUNC0);
257 mmio_write_32(IOMG_SD_DATA2, IOMG_MUX_FUNC0);
258 mmio_write_32(IOMG_SD_DATA3, IOMG_MUX_FUNC0);
259
260 mmio_write_32(IOCG_SD_CLK, IOCG_INPUT_16MA);
261 mmio_write_32(IOCG_SD_CMD, IOCG_INPUT_12MA);
262 mmio_write_32(IOCG_SD_DATA0, IOCG_INPUT_12MA);
263 mmio_write_32(IOCG_SD_DATA1, IOCG_INPUT_12MA);
264 mmio_write_32(IOCG_SD_DATA2, IOCG_INPUT_12MA);
265 mmio_write_32(IOCG_SD_DATA3, IOCG_INPUT_12MA);
266
267 /* set SD Card detect as nopull */
268 mmio_write_32(IOCG_GPIO8, 0);
269}
270
271static void hikey_jumper_init(void)
272{
273 /* set jumper detect as nopull */
274 mmio_write_32(IOCG_GPIO24, 0);
275 /* set jumper detect as GPIO */
276 mmio_write_32(IOMG_GPIO24, IOMG_MUX_FUNC0);
277}
278
Haojian Zhuangb755da32018-01-25 16:10:14 +0800279void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
280 u_register_t arg3, u_register_t arg4)
281{
Haojian Zhuang934ae712017-05-24 08:47:49 +0800282 /* Initialize the console to provide early debug support */
Jerome Forissieraebe95d2018-11-08 10:17:47 +0000283 console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ,
284 PL011_BAUDRATE, &console);
Haojian Zhuangb755da32018-01-25 16:10:14 +0800285 /*
286 * Allow BL2 to see the whole Trusted RAM.
287 */
288 bl2_el3_tzram_layout.total_base = BL2_RW_BASE;
289 bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE;
290}
Haojian Zhuang934ae712017-05-24 08:47:49 +0800291
Haojian Zhuangb755da32018-01-25 16:10:14 +0800292void bl2_el3_plat_arch_setup(void)
293{
294 hikey_init_mmu_el3(bl2_el3_tzram_layout.total_base,
295 bl2_el3_tzram_layout.total_size,
296 BL2_RO_BASE,
297 BL2_RO_LIMIT,
298 BL2_COHERENT_RAM_BASE,
299 BL2_COHERENT_RAM_LIMIT);
300}
Haojian Zhuang934ae712017-05-24 08:47:49 +0800301
Haojian Zhuangb755da32018-01-25 16:10:14 +0800302void bl2_platform_setup(void)
303{
304 dw_mmc_params_t params;
Haojian Zhuange9713772018-08-04 18:07:10 +0800305 struct mmc_device_info info;
Haojian Zhuang934ae712017-05-24 08:47:49 +0800306
Haojian Zhuangb755da32018-01-25 16:10:14 +0800307 hikey_sp804_init();
308 hikey_gpio_init();
309 hikey_pmussi_init();
310 hikey_hi6553_init();
Haojian Zhuanga403c3a2018-04-11 19:06:14 +0800311 /* Clear SRAM since it'll be used by MCU right now. */
312 memset((void *)SRAM_BASE, 0, SRAM_SIZE);
Haojian Zhuangb755da32018-01-25 16:10:14 +0800313
Haojian Zhuang934ae712017-05-24 08:47:49 +0800314 dsb();
Haojian Zhuange18de672018-04-11 19:05:32 +0800315 hikey_ddr_init(DDR_FREQ_800M);
Haojian Zhuangb755da32018-01-25 16:10:14 +0800316 hikey_security_setup();
317
Haojian Zhuang934ae712017-05-24 08:47:49 +0800318 hikey_boardid_init();
319 init_acpu_dvfs();
Haojian Zhuangb755da32018-01-25 16:10:14 +0800320 hikey_rtc_init();
Haojian Zhuang934ae712017-05-24 08:47:49 +0800321 hikey_sd_init();
322 hikey_jumper_init();
323
Haojian Zhuangb755da32018-01-25 16:10:14 +0800324 hikey_mmc_pll_init();
325
Haojian Zhuanga403c3a2018-04-11 19:06:14 +0800326 /* Clean SRAM before MCU used */
327 clean_dcache_range(SRAM_BASE, SRAM_SIZE);
328
Haojian Zhuang934ae712017-05-24 08:47:49 +0800329 reset_dwmmc_clk();
330 memset(&params, 0, sizeof(dw_mmc_params_t));
331 params.reg_base = DWMMC0_BASE;
332 params.desc_base = HIKEY_MMC_DESC_BASE;
333 params.desc_size = 1 << 20;
334 params.clk_rate = 24 * 1000 * 1000;
Haojian Zhuange9713772018-08-04 18:07:10 +0800335 params.bus_width = MMC_BUS_WIDTH_8;
336 params.flags = MMC_FLAG_CMD23;
337 info.mmc_dev_type = MMC_IS_EMMC;
338 dw_mmc_init(&params, &info);
Ryan Grachek708c2ee2018-11-15 08:41:25 -0600339 mdelay(20);
Haojian Zhuang934ae712017-05-24 08:47:49 +0800340
341 hikey_io_setup();
342}