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git01.mediatek.com / filogic / atf / b86acb02ebea5a4e1b050dde6ad55fb989483595 / . / lib / aarch64 / xlat_helpers.c
blob: d401ffc42409decc1e88dce8b19809b2d3615967 [file] [log] [blame]
Achin Guptaa0cd9892014-02-09 13:30:38 +0000[diff] [blame]1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Guptaa0cd9892014-02-09 13:30:38 +0000[diff] [blame]31#include <arch.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +0100[diff] [blame]32#include <assert.h>
Achin Guptaa0cd9892014-02-09 13:30:38 +0000[diff] [blame]33
34/*******************************************************************************
35 * Helper to create a level 1/2 table descriptor which points to a level 2/3
36 * table.
37 ******************************************************************************/
38unsigned long create_table_desc(unsigned long *next_table_ptr)
39{
40 unsigned long desc = (unsigned long) next_table_ptr;
41
42 /* Clear the last 12 bits */
43 desc >>= FOUR_KB_SHIFT;
44 desc <<= FOUR_KB_SHIFT;
45
46 desc |= TABLE_DESC;
47
48 return desc;
49}
50
51/*******************************************************************************
52 * Helper to create a level 1/2/3 block descriptor which maps the va to addr
53 ******************************************************************************/
54unsigned long create_block_desc(unsigned long desc,
55 unsigned long addr,
56 unsigned int level)
57{
58 switch (level) {
59 case LEVEL1:
60 desc |= (addr << FIRST_LEVEL_DESC_N) | BLOCK_DESC;
61 break;
62 case LEVEL2:
63 desc |= (addr << SECOND_LEVEL_DESC_N) | BLOCK_DESC;
64 break;
65 case LEVEL3:
66 desc |= (addr << THIRD_LEVEL_DESC_N) | TABLE_DESC;
67 break;
68 default:
69 assert(0);
70 }
71
72 return desc;
73}
74
75/*******************************************************************************
76 * Helper to create a level 1/2/3 block descriptor which maps the va to output_
77 * addr with Device nGnRE attributes.
78 ******************************************************************************/
79unsigned long create_device_block(unsigned long output_addr,
80 unsigned int level,
81 unsigned int ns)
82{
83 unsigned long upper_attrs, lower_attrs, desc;
84
85 lower_attrs = LOWER_ATTRS(ACCESS_FLAG | OSH | AP_RW);
86 lower_attrs |= LOWER_ATTRS(ns | ATTR_DEVICE_INDEX);
87 upper_attrs = UPPER_ATTRS(XN);
88 desc = upper_attrs | lower_attrs;
89
90 return create_block_desc(desc, output_addr, level);
91}
92
93/*******************************************************************************
94 * Helper to create a level 1/2/3 block descriptor which maps the va to output_
95 * addr with inner-shareable normal wbwa read-only memory attributes.
96 ******************************************************************************/
97unsigned long create_romem_block(unsigned long output_addr,
98 unsigned int level,
99 unsigned int ns)
100{
101 unsigned long upper_attrs, lower_attrs, desc;
102
103 lower_attrs = LOWER_ATTRS(ACCESS_FLAG | ISH | AP_RO);
104 lower_attrs |= LOWER_ATTRS(ns | ATTR_IWBWA_OWBWA_NTR_INDEX);
105 upper_attrs = UPPER_ATTRS(0ull);
106 desc = upper_attrs | lower_attrs;
107
108 return create_block_desc(desc, output_addr, level);
109}
110
111/*******************************************************************************
112 * Helper to create a level 1/2/3 block descriptor which maps the va to output_
113 * addr with inner-shareable normal wbwa read-write memory attributes.
114 ******************************************************************************/
115unsigned long create_rwmem_block(unsigned long output_addr,
116 unsigned int level,
117 unsigned int ns)
118{
119 unsigned long upper_attrs, lower_attrs, desc;
120
121 lower_attrs = LOWER_ATTRS(ACCESS_FLAG | ISH | AP_RW);
122 lower_attrs |= LOWER_ATTRS(ns | ATTR_IWBWA_OWBWA_NTR_INDEX);
123 upper_attrs = UPPER_ATTRS(XN);
124 desc = upper_attrs | lower_attrs;
125
126 return create_block_desc(desc, output_addr, level);
127}