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Deepak Pandey9cbacf62018-08-08 10:32:51 +05301/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Deepak Pandey9cbacf62018-08-08 10:32:51 +05309
10#include <arm_def.h>
11#include <board_css_def.h>
12#include <css_def.h>
13
14#if CSS_USE_SCMI_SDS_DRIVER
15#define N1SDP_SCMI_PAYLOAD_BASE 0x45400000
16#else
17#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000
18#endif
19
20#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
21#define PLAT_ARM_MAX_BL31_SIZE 0X20000
22
23
24/*******************************************************************************
25 * N1SDP topology related constants
26 ******************************************************************************/
27#define N1SDP_MAX_CPUS_PER_CLUSTER 2
28#define PLAT_ARM_CLUSTER_COUNT 2
29#define N1SDP_MAX_PE_PER_CPU 1
30
31#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
32 N1SDP_MAX_CPUS_PER_CLUSTER * \
33 N1SDP_MAX_PE_PER_CPU)
34
Chandni Cherukuri0fdcbc02018-10-16 15:19:54 +053035/* System power domain level */
36#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
Deepak Pandey9cbacf62018-08-08 10:32:51 +053037
38/*
39 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
40 * plat_arm_mmap array defined for each BL stage.
41 */
42#define PLAT_ARM_MMAP_ENTRIES 3
43#define MAX_XLAT_TABLES 4
44
45#define PLATFORM_STACK_SIZE 0x400
46
47#define PLAT_ARM_NSTIMER_FRAME_ID 0
48#define PLAT_CSS_MHU_BASE 0x45000000
49#define PLAT_MAX_PWR_LVL 1
50
51#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \
52 CSS_IRQ_MHU
53#define PLAT_ARM_G0_IRQS ARM_G0_IRQS
54
55#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
56#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
57
58
59#define N1SDP_DEVICE_BASE (0x20000000)
60#define N1SDP_DEVICE_SIZE (0x20000000)
61#define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \
62 N1SDP_DEVICE_BASE, \
63 N1SDP_DEVICE_SIZE, \
64 MT_DEVICE | MT_RW | MT_SECURE)
65
66/* GIC related constants */
67#define PLAT_ARM_GICD_BASE 0x30000000
68#define PLAT_ARM_GICC_BASE 0x2C000000
69#define PLAT_ARM_GICR_BASE 0x300C0000
70
71/* Platform ID address */
72#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000073
74#endif /* PLATFORM_DEF_H */